2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
34 * High Level Configuration Options
38 #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
39 #define CONFIG_PM828 1 /* ...on a PM828 module */
41 #undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
43 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
45 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
47 #undef CONFIG_BOOTARGS
48 #define CONFIG_BOOTCOMMAND \
50 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
51 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
54 /* enable I2C and select the hardware/software driver */
55 #undef CONFIG_HARD_I2C
56 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
57 # define CFG_I2C_SPEED 50000
58 # define CFG_I2C_SLAVE 0xFE
60 * Software (bit-bang) I2C driver configuration
62 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
63 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
64 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
65 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
66 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
67 else iop->pdat &= ~0x00010000
68 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
69 else iop->pdat &= ~0x00020000
70 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
73 #define CONFIG_RTC_PCF8563
74 #define CFG_I2C_RTC_ADDR 0x51
77 * select serial console configuration
79 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
80 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
83 * if CONFIG_CONS_NONE is defined, then the serial console routines must
84 * defined elsewhere (for example, on the cogent platform, there are serial
85 * ports on the motherboard which are used for the serial console - see
86 * cogent/cma101/serial.[ch]).
88 #define CONFIG_CONS_ON_SMC /* define if console on SMC */
89 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
90 #undef CONFIG_CONS_NONE /* define if console on something else*/
91 #define CONFIG_CONS_INDEX 2 /* which serial channel for console */
94 * select ethernet configuration
96 * if CONFIG_ETHER_ON_SCC is selected, then
97 * - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
98 * - CONFIG_NET_MULTI must not be defined
100 * if CONFIG_ETHER_ON_FCC is selected, then
101 * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
102 * - CONFIG_NET_MULTI must be defined
104 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
105 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
106 * from CONFIG_COMMANDS to remove support for networking.
108 #define CONFIG_NET_MULTI
109 #undef CONFIG_ETHER_NONE /* define if ether on something else */
111 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
112 #define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
114 #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
119 #define CONFIG_ETHER_ON_FCC1
120 # define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
121 #ifndef CONFIG_DB_CR826_J30x_ON
122 # define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
124 # define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
130 #define CONFIG_ETHER_ON_FCC2
131 # define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
132 # define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
134 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
135 * - Enable Full Duplex in FSMR
137 # define CFG_CPMFCR_RAMTYPE 0
138 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
140 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
141 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
143 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
144 #define CONFIG_BAUDRATE 230400
146 #define CONFIG_BAUDRATE 9600
149 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
150 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
152 #undef CONFIG_WATCHDOG /* watchdog disabled */
154 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
157 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
168 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
177 #endif /* CONFIG_PCI */
179 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
180 #include <cmd_confdefs.h>
183 * Disk-On-Chip configuration
186 #define CFG_DOC_SHORT_TIMEOUT
187 #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
189 #define CFG_DOC_SUPPORT_2000
190 #define CFG_DOC_SUPPORT_MILLENNIUM
193 * Miscellaneous configurable options
195 #define CFG_LONGHELP /* undef to save memory */
196 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
197 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
198 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
200 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
202 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
203 #define CFG_MAXARGS 16 /* max number of command args */
204 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
206 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
207 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
209 #define CFG_LOAD_ADDR 0x100000 /* default load address */
211 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
213 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
215 #define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
218 * For booting Linux, the board info and command line data
219 * have to be in the first 8 MB of memory, since this is
220 * the maximum mapped by the Linux kernel during initialization.
222 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
224 /*-----------------------------------------------------------------------
225 * Flash and Boot ROM mapping
228 #define CFG_BOOTROM_BASE 0xFF800000
229 #define CFG_BOOTROM_SIZE 0x00080000
230 #define CFG_FLASH0_BASE 0x40000000
231 #define CFG_FLASH0_SIZE 0x02000000
232 #define CFG_DOC_BASE 0xFF800000
233 #define CFG_DOC_SIZE 0x00100000
236 /* Flash bank size (for preliminary settings)
238 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
240 /*-----------------------------------------------------------------------
243 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
244 #define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
246 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
247 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
250 /* Start port with environment in flash; switch to EEPROM later */
251 #define CFG_ENV_IS_IN_FLASH 1
252 #define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
253 #define CFG_ENV_SIZE 0x40000
254 #define CFG_ENV_SECT_SIZE 0x40000
256 /* Final version: environment in EEPROM */
257 #define CFG_ENV_IS_IN_EEPROM 1
258 #define CFG_I2C_EEPROM_ADDR 0x58
259 #define CFG_I2C_EEPROM_ADDR_LEN 1
260 #define CFG_EEPROM_PAGE_WRITE_BITS 4
261 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
262 #define CFG_ENV_OFFSET 512
263 #define CFG_ENV_SIZE (2048 - 512)
266 /*-----------------------------------------------------------------------
267 * Hard Reset Configuration Words
269 * if you change bits in the HRCW, you must also change the CFG_*
270 * defines for the various registers affected by the HRCW e.g. changing
271 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
273 #if defined(CONFIG_BOOT_ROM)
274 #define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
276 #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
279 /* no slaves so just fill with zeros */
280 #define CFG_HRCW_SLAVE1 0
281 #define CFG_HRCW_SLAVE2 0
282 #define CFG_HRCW_SLAVE3 0
283 #define CFG_HRCW_SLAVE4 0
284 #define CFG_HRCW_SLAVE5 0
285 #define CFG_HRCW_SLAVE6 0
286 #define CFG_HRCW_SLAVE7 0
288 /*-----------------------------------------------------------------------
289 * Internal Memory Mapped Register
291 #define CFG_IMMR 0xF0000000
293 /*-----------------------------------------------------------------------
294 * Definitions for initial stack pointer and data area (in DPRAM)
296 #define CFG_INIT_RAM_ADDR CFG_IMMR
297 #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
298 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
299 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
300 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
302 /*-----------------------------------------------------------------------
303 * Start addresses for the final memory configuration
304 * (Set up by the startup code)
305 * Please note that CFG_SDRAM_BASE _must_ start at 0
307 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
308 * is mapped at SDRAM_BASE2_PRELIM.
310 #define CFG_SDRAM_BASE 0x00000000
311 #define CFG_FLASH_BASE CFG_FLASH0_BASE
312 #define CFG_MONITOR_BASE TEXT_BASE
313 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
314 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
316 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
321 #define CONFIG_PCI_PNP
322 #define CONFIG_EEPRO100
323 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
327 * Internal Definitions
331 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
332 #define BOOTFLAG_WARM 0x02 /* Software reboot */
335 /*-----------------------------------------------------------------------
336 * Cache Configuration
338 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
339 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
340 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
343 /*-----------------------------------------------------------------------
344 * HIDx - Hardware Implementation-dependent Registers 2-11
345 *-----------------------------------------------------------------------
346 * HID0 also contains cache control - initially enable both caches and
347 * invalidate contents, then the final state leaves only the instruction
348 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
349 * but Soft reset does not.
351 * HID1 has only read-only information - nothing to set.
353 #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
355 #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
358 /*-----------------------------------------------------------------------
359 * RMR - Reset Mode Register 5-5
360 *-----------------------------------------------------------------------
361 * turn on Checkstop Reset Enable
363 #define CFG_RMR RMR_CSRE
365 /*-----------------------------------------------------------------------
366 * BCR - Bus Configuration 4-25
367 *-----------------------------------------------------------------------
370 #define BCR_APD01 0x10000000
371 #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
373 /*-----------------------------------------------------------------------
374 * SIUMCR - SIU Module Configuration 4-31
375 *-----------------------------------------------------------------------
378 #define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
380 #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
384 /*-----------------------------------------------------------------------
385 * SYPCR - System Protection Control 4-35
386 * SYPCR can only be written once after reset!
387 *-----------------------------------------------------------------------
388 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
390 #if defined(CONFIG_WATCHDOG)
391 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
392 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
394 #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
395 SYPCR_SWRI|SYPCR_SWP)
396 #endif /* CONFIG_WATCHDOG */
398 /*-----------------------------------------------------------------------
399 * TMCNTSC - Time Counter Status and Control 4-40
400 *-----------------------------------------------------------------------
401 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
402 * and enable Time Counter
404 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
406 /*-----------------------------------------------------------------------
407 * PISCR - Periodic Interrupt Status and Control 4-42
408 *-----------------------------------------------------------------------
409 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
412 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
414 /*-----------------------------------------------------------------------
415 * SCCR - System Clock Control 9-8
416 *-----------------------------------------------------------------------
418 #define CFG_SCCR (SCCR_DFBRG00)
420 /*-----------------------------------------------------------------------
421 * RCCR - RISC Controller Configuration 13-7
422 *-----------------------------------------------------------------------
427 * Init Memory Controller:
429 * Bank Bus Machine PortSz Device
430 * ---- --- ------- ------ ------
431 * 0 60x GPCM 64 bit FLASH
432 * 1 60x SDRAM 64 bit SDRAM
436 /* Initialize SDRAM on local bus
438 #define CFG_INIT_LOCAL_SDRAM
441 /* Minimum mask to separate preliminary
442 * address ranges for CS[0:2]
444 #define CFG_MIN_AM_MASK 0xC0000000
447 * we use the same values for 32 MB and 128 MB SDRAM
448 * refresh rate = 7.68 uS (100 MHz Bus Clock)
450 #define CFG_MPTPR 0x2000
451 #define CFG_PSRT 0x16
453 #define CFG_MRS_OFFS 0x00000000
456 #if defined(CONFIG_BOOT_ROM)
458 * Bank 0 - Boot ROM (8 bit wide)
460 #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
465 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
473 * Bank 1 - Flash (64 bit wide)
475 #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
480 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
487 #else /* ! CONFIG_BOOT_ROM */
490 * Bank 0 - Flash (64 bit wide)
492 #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
497 #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
505 * Bank 1 - Disk-On-Chip
507 #define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
512 #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
519 #endif /* CONFIG_BOOT_ROM */
525 #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
530 /* SDRAM initialization values for 8-column chips
532 #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
534 ORxS_ROWST_PBI0_A9 |\
537 #define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
538 PSDMR_BSMA_A14_A16 |\
539 PSDMR_SDA10_PBI0_A10 |\
547 /* SDRAM initialization values for 9-column chips
549 #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
551 ORxS_ROWST_PBI0_A7 |\
554 #define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
555 PSDMR_BSMA_A13_A15 |\
556 PSDMR_SDA10_PBI0_A9 |\
564 #define CFG_OR2_PRELIM CFG_OR2_9COL
565 #define CFG_PSDMR CFG_PSDMR_9COL
567 #endif /* CFG_RAMBOOT */
569 #endif /* __CONFIG_H */