2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_PMC405 1 /* ...on a PMC405 board */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
43 #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
45 #define CONFIG_BAUDRATE 9600
46 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48 #undef CONFIG_BOOTARGS
49 #undef CONFIG_BOOTCOMMAND
51 #define CONFIG_PREBOOT /* enable preboot variable */
53 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
54 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
56 #define CONFIG_NET_MULTI 1
57 #undef CONFIG_HAS_ETH1
59 #define CONFIG_PPC4xx_EMAC
60 #define CONFIG_MII 1 /* MII PHY management */
61 #define CONFIG_PHY_ADDR 0 /* PHY address */
62 #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
63 #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
65 #define CONFIG_NETCONSOLE /* include NetConsole support */
71 #define CONFIG_BOOTP_BOOTFILESIZE
72 #define CONFIG_BOOTP_BOOTPATH
73 #define CONFIG_BOOTP_GATEWAY
74 #define CONFIG_BOOTP_HOSTNAME
78 * Command line configuration.
80 #include <config_cmd_default.h>
82 #define CONFIG_CMD_BSP
83 #define CONFIG_CMD_PCI
84 #define CONFIG_CMD_IRQ
85 #define CONFIG_CMD_ELF
86 #define CONFIG_CMD_DATE
87 #define CONFIG_CMD_JFFS2
88 #define CONFIG_CMD_MII
89 #define CONFIG_CMD_I2C
90 #define CONFIG_CMD_PING
91 #define CONFIG_CMD_UNIVERSE
92 #define CONFIG_CMD_EEPROM
95 #define CONFIG_MAC_PARTITION
96 #define CONFIG_DOS_PARTITION
98 #undef CONFIG_WATCHDOG /* watchdog disabled */
100 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
101 #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
103 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
106 * Miscellaneous configurable options
108 #define CONFIG_SYS_LONGHELP /* undef to save memory */
109 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
111 #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
112 #ifdef CONFIG_SYS_HUSH_PARSER
113 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
116 #if defined(CONFIG_CMD_KGDB)
117 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
119 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
121 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
122 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
123 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
125 #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
127 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
129 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
131 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
132 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
134 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
135 #define CONFIG_SYS_BASE_BAUD 691200
137 /* The following table includes the supported baudrates */
138 #define CONFIG_SYS_BAUDRATE_TABLE \
139 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
140 57600, 115200, 230400, 460800, 921600 }
142 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
143 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
145 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
147 #define CONFIG_LOOPW 1 /* enable loopw command */
149 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
151 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
153 #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
155 /*-----------------------------------------------------------------------
157 *-----------------------------------------------------------------------
159 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
160 #define PCI_HOST_FORCE 1 /* configure as pci host */
161 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
163 #define CONFIG_PCI /* include pci support */
164 #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
165 #define CONFIG_PCI_PNP /* do pci plug-and-play */
166 /* resource configuration */
168 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
170 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
172 #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
174 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
175 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */
176 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */
177 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
179 #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
181 #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
182 #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
183 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
185 #define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
186 #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
187 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
188 #else /* old mapping */
189 #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
190 #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
191 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
193 /*-----------------------------------------------------------------------
194 * Start addresses for the final memory configuration
195 * (Set up by the startup code)
196 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
198 #define CONFIG_SYS_SDRAM_BASE 0x00000000
199 #define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
200 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
201 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
204 * For booting Linux, the board info and command line data
205 * have to be in the first 8 MB of memory, since this is
206 * the maximum mapped by the Linux kernel during initialization.
208 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
210 /*-----------------------------------------------------------------------
213 #define CONFIG_SYS_FLASH_BASE 0xFE000000
214 #define CONFIG_SYS_FLASH_INCREMENT 0x01000000
216 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
217 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
218 #define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
219 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
220 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
221 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT }
222 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
224 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
227 * JFFS2 partitions - second bank contains u-boot
230 /* No command line, one static partition, whole device */
231 #undef CONFIG_JFFS2_CMDLINE
232 #define CONFIG_JFFS2_DEV "nor0"
233 #define CONFIG_JFFS2_PART_SIZE 0x01b00000
234 #define CONFIG_JFFS2_PART_OFFSET 0x00400000
236 /* mtdparts command line support */
237 /* Note: fake mtd_id used, no linux mtd map file */
239 #define CONFIG_JFFS2_CMDLINE
240 #define MTDIDS_DEFAULT "nor0=pmc405-0"
241 #define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)"
244 /*-----------------------------------------------------------------------
245 * Environment Variable setup
247 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
248 #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
249 #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
250 /* total size of a CAT24WC16 is 2048 bytes */
252 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
253 #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
255 /*-----------------------------------------------------------------------
256 * I2C EEPROM (CAT24WC16) for environment
258 #define CONFIG_HARD_I2C /* I2c with hardware support */
259 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
260 #define CONFIG_SYS_I2C_SLAVE 0x7F
262 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
263 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
264 /* mask of address bits that overflow into the "EEPROM chip address" */
265 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
267 /* 16 byte page write mode using*/
268 /* last 4 bits of the address */
269 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
271 /*-----------------------------------------------------------------------
272 * External Bus Controller (EBC) Setup
274 #define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
275 #define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
276 #define CAN_BA 0xF0000000 /* CAN Base Address */
277 #define RTC_BA 0xF0000500 /* RTC Base Address */
278 #define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
280 /* Memory Bank 0 (Flash Bank 0) initialization */
281 #define CONFIG_SYS_EBC_PB0AP 0x92015480
282 #define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
284 /* Memory Bank 1 (Flash Bank 1) initialization */
285 #define CONFIG_SYS_EBC_PB1AP 0x92015480
286 #define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
288 /* Memory Bank 2 (CAN0, 1, RTC) initialization */
289 #define CONFIG_SYS_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
290 #define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
292 /* Memory Bank 3 -> unused */
294 /* Memory Bank 4 (NVRAM) initialization */
295 #define CONFIG_SYS_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
296 #define CONFIG_SYS_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
298 /*-----------------------------------------------------------------------
301 #define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
302 #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
304 /* FPGA program pin configuration */
305 #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
306 #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
307 #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
308 #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
309 #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
311 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
313 /*-----------------------------------------------------------------------
316 #define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO24 */
317 #define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
318 #define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
319 #define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
320 #define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
322 /*-----------------------------------------------------------------------
323 * Definitions for initial stack pointer and data area (in data cache)
326 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
327 #define CONFIG_SYS_TEMP_STACK_OCM 1
329 /* On Chip Memory location */
330 #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
331 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
333 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
334 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
335 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
336 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
337 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
340 * Internal Definitions
344 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
345 #define BOOTFLAG_WARM 0x02 /* Software reboot */
347 #endif /* __CONFIG_H */