2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
34 #undef __DEBUG_START_FROM_SRAM__
35 #define __DISABLE_MACHINE_EXCEPTION__
37 #ifdef __DEBUG_START_FROM_SRAM__
38 #define CFG_DUMMY_FLASH_SIZE 1024*1024*4
42 * High Level Configuration Options
46 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
47 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
48 #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
50 #define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
51 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
53 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
56 #define CONFIG_BAUDRATE 9600
58 #define CONFIG_BAUDRATE 115200
60 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
63 #define CONFIG_PREBOOT \
64 "crc32 f0207004 ffc 0;" \
65 "if cmp 0 f0207000 1;" \
66 "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;" \
67 "else;echo Old CRC is bad;fi"
70 #undef CONFIG_BOOTARGS
71 #define CONFIG_RAMBOOTCOMMAND \
72 "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
73 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
74 "bootm ffc00000 ffca0000"
75 #define CONFIG_NFSBOOTCOMMAND \
76 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
77 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
80 #define CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND \
81 "setenv ipaddr 192.168.10.203;" \
82 "setenv serverip 192.168.10.6;" \
83 "setenv netmask 255.255.255.0;" \
84 "setenv bootargs root=/dev/ram rw console=ttyS0,9600;" \
85 "setenv autostart yes;" \
86 "bootm ffc00000 ffd00000"
88 "setenv ethaddr 00:50:c2:1e:af:fe;" \
89 "setenv eth1addr 00:50:c2:1e:af:fd;" \
92 #define CONFIG_BOOTCOMMAND CONFIG_PELK_NOR_KERNEL_NOR_RAMDISK_BOOTCOMMAND
94 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
95 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
99 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
100 #define CONFIG_ETHADDR 00:50:c2:1e:af:fe
101 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
103 #undef CONFIG_EXT_PHY
104 /*#define CONFIG_EXT_PHY*/
105 #define CONFIG_MII 1 /* MII PHY management */
106 #ifndef CONFIG_EXT_PHY
107 #define CONFIG_PHY_ADDR 1 /* PHY address */
109 #define CONFIG_PHY_ADDR 2 /* PHY address */
111 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
113 #if 0 /* test-only */
114 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
122 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
132 #define CONFIG_MAC_PARTITION
133 #define CONFIG_DOS_PARTITION
135 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
136 #include <cmd_confdefs.h>
138 #undef CONFIG_WATCHDOG /* watchdog disabled */
140 #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
141 #define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
143 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
146 * Miscellaneous configurable options
148 #define CFG_LONGHELP /* undef to save memory */
149 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
151 #undef CFG_HUSH_PARSER /* use "hush" command parser */
152 #ifdef CFG_HUSH_PARSER
153 #define CFG_PROMPT_HUSH_PS2 "> "
156 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
157 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
159 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
161 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
162 #define CFG_MAXARGS 16 /* max number of command args */
163 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
165 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
167 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
169 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
170 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
172 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
173 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
174 #define CFG_BASE_BAUD 691200
176 /* The following table includes the supported baudrates */
177 #define CFG_BAUDRATE_TABLE \
178 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
179 57600, 115200, 230400, 460800, 921600 }
181 #define CFG_LOAD_ADDR 0x100000 /* default load address */
182 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
184 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
186 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
188 /*-----------------------------------------------------------------------
190 *-----------------------------------------------------------------------
192 #define CFG_NAND0_BASE 0xFF400000
193 #define CFG_NAND1_BASE 0xFF000000
195 #define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
196 #define SECTORSIZE 512
198 #define ADDR_COLUMN 1
200 #define ADDR_COLUMN_PAGE 3
202 #define NAND_ChipID_UNKNOWN 0x00
203 #define NAND_MAX_FLOORS 1
204 #define NAND_MAX_CHIPS 1
206 #define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
207 #define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
208 #define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
209 #define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
211 #define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
212 #define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
213 #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
214 #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
217 #define NAND_DISABLE_CE(nand) do \
219 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
221 case CFG_NAND0_BASE: \
222 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
224 case CFG_NAND1_BASE: \
225 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
230 #define NAND_ENABLE_CE(nand) do \
232 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
234 case CFG_NAND0_BASE: \
235 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
237 case CFG_NAND1_BASE: \
238 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
245 #define NAND_CTL_CLRALE(nandptr) do \
247 switch((unsigned long)nandptr) \
249 case CFG_NAND0_BASE: \
250 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
252 case CFG_NAND1_BASE: \
253 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
258 #define NAND_CTL_SETALE(nandptr) do \
260 switch((unsigned long)nandptr) \
262 case CFG_NAND0_BASE: \
263 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
265 case CFG_NAND1_BASE: \
266 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
271 #define NAND_CTL_CLRCLE(nandptr) do \
273 switch((unsigned long)nandptr) \
275 case CFG_NAND0_BASE: \
276 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
278 case CFG_NAND1_BASE: \
279 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
284 #define NAND_CTL_SETCLE(nandptr) do { \
285 switch((unsigned long)nandptr) { \
286 case CFG_NAND0_BASE: \
287 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
289 case CFG_NAND1_BASE: \
290 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
295 #define NAND_WAIT_READY(nand) do { \
297 switch ((ulong)(((struct nand_chip *)nand)->IO_ADDR)) { \
298 case CFG_NAND0_BASE: \
299 mask = CFG_NAND0_RDY; \
301 case CFG_NAND1_BASE: \
302 mask = CFG_NAND1_RDY; \
305 while (!(in32(GPIO0_IR) & mask)) \
309 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
310 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
311 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
312 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
314 /*-----------------------------------------------------------------------
316 *-----------------------------------------------------------------------
318 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
319 #define PCI_HOST_FORCE 1 /* configure as pci host */
320 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
322 #define CONFIG_PCI /* include pci support */
323 #define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
324 #undef CONFIG_PCI_PNP /* do pci plug-and-play */
325 /* resource configuration */
327 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
329 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
330 #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
331 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
332 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
333 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
334 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
335 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
336 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
337 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
339 /*-----------------------------------------------------------------------
340 * Start addresses for the final memory configuration
341 * (Set up by the startup code)
342 * Please note that CFG_SDRAM_BASE _must_ start at 0
344 #define CFG_SDRAM_BASE 0x00000000
345 #define CFG_FLASH_BASE 0xFFFC0000
346 #define CFG_MONITOR_BASE CFG_FLASH_BASE
347 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
348 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
351 * For booting Linux, the board info and command line data
352 * have to be in the first 8 MB of memory, since this is
353 * the maximum mapped by the Linux kernel during initialization.
355 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
356 /*-----------------------------------------------------------------------
359 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
360 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
362 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
363 #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
365 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
366 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
367 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
369 * The following defines are added for buggy IOP480 byte interface.
370 * All other boards should use the standard values (CPCI405 etc.)
372 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
373 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
374 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
376 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
378 #if 0 /* test-only */
379 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
380 #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
383 /*-----------------------------------------------------------------------
384 * Environment Variable setup
386 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
387 #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
388 #define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
389 /* total size of a CAT24WC16 is 2048 bytes */
391 #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
392 #define CFG_NVRAM_SIZE 242 /* NVRAM size */
394 /*-----------------------------------------------------------------------
395 * I2C EEPROM (CAT24WC16) for environment
397 #define CONFIG_HARD_I2C /* I2c with hardware support */
398 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
399 #define CFG_I2C_SLAVE 0x7F
401 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
402 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
403 /* mask of address bits that overflow into the "EEPROM chip address" */
404 /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
405 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
406 /* 16 byte page write mode using*/
407 /* last 4 bits of the address */
408 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
409 #define CFG_EEPROM_PAGE_WRITE_ENABLE
411 /*-----------------------------------------------------------------------
412 * Cache Configuration
414 #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
415 /* have only 8kB, 16kB is save here */
416 #define CFG_CACHELINE_SIZE 32 /* ... */
417 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
418 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
422 * Init Memory Controller:
424 * BR0/1 and OR0/1 (FLASH)
427 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
429 /*-----------------------------------------------------------------------
430 * External Bus Controller (EBC) Setup
433 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
434 #define CFG_EBC_PB0AP 0x92015480
435 #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
437 /* Memory Bank 1 (External SRAM) initialization */
438 /* Since this must replace NOR Flash, we use the same settings for CS0 */
439 #define CFG_EBC_PB1AP 0x92015480
440 #define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
442 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
443 #define CFG_EBC_PB2AP 0x92015480
444 #define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
446 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
447 #define CFG_EBC_PB3AP 0x92015480
448 #define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
452 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
453 #define CFG_EBC_PB1AP 0x92015480
454 #define CFG_EBC_PB1CR 0xFF858000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
456 /* Memory Bank 2 (CAN0, 1) initialization */
457 #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
458 #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
460 /* Memory Bank 3 (CompactFlash IDE) initialization */
461 #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
462 #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
464 /* Memory Bank 4 (NVRAM/RTC) initialization */
465 #define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
466 #define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
469 /*-----------------------------------------------------------------------
472 /* FPGA internal regs */
473 #define CFG_FPGA_MODE 0x00
474 #define CFG_FPGA_STATUS 0x02
475 #define CFG_FPGA_TS 0x04
476 #define CFG_FPGA_TS_LOW 0x06
477 #define CFG_FPGA_TS_CAP0 0x10
478 #define CFG_FPGA_TS_CAP0_LOW 0x12
479 #define CFG_FPGA_TS_CAP1 0x14
480 #define CFG_FPGA_TS_CAP1_LOW 0x16
481 #define CFG_FPGA_TS_CAP2 0x18
482 #define CFG_FPGA_TS_CAP2_LOW 0x1a
483 #define CFG_FPGA_TS_CAP3 0x1c
484 #define CFG_FPGA_TS_CAP3_LOW 0x1e
487 #define CFG_FPGA_MODE_CF_RESET 0x0001
488 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
489 #define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
490 #define CFG_FPGA_MODE_TS_CLEAR 0x2000
492 /* FPGA Status Reg */
493 #define CFG_FPGA_STATUS_DIP0 0x0001
494 #define CFG_FPGA_STATUS_DIP1 0x0002
495 #define CFG_FPGA_STATUS_DIP2 0x0004
496 #define CFG_FPGA_STATUS_FLASH 0x0008
497 #define CFG_FPGA_STATUS_TS_IRQ 0x1000
499 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
500 #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
502 /* FPGA program pin configuration */
503 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
504 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
505 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
506 #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
507 #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
509 /*-----------------------------------------------------------------------
510 * Definitions for initial stack pointer and data area (in data cache)
512 #if 0 /* test-only */
513 #define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
515 #define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
516 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
518 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
519 #define CFG_TEMP_STACK_OCM 1
521 /* On Chip Memory location */
522 #define CFG_OCM_DATA_ADDR 0xF8000000
523 #define CFG_OCM_DATA_SIZE 0x1000
524 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
525 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
528 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
529 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
530 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
532 /*-----------------------------------------------------------------------
533 * Definitions for GPIO setup (PPC405EP specific)
535 * GPIO0[0] - External Bus Controller BLAST output
536 * GPIO0[1-9] - Instruction trace outputs -> GPIO
537 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
538 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
539 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
540 * GPIO0[24-27] - UART0 control signal inputs/outputs
541 * GPIO0[28-29] - UART1 data signal input/output
542 * GPIO0[30] - EMAC0 input
543 * GPIO0[31] - EMAC1 reject packet as output
545 #define CFG_GPIO0_OSRH 0x40000550
546 #define CFG_GPIO0_OSRL 0x00000110
547 #define CFG_GPIO0_ISR1H 0x00000000
548 /*#define CFG_GPIO0_ISR1L 0x15555445*/
549 #define CFG_GPIO0_ISR1L 0x15555444
550 #define CFG_GPIO0_TSRH 0x00000000
551 #define CFG_GPIO0_TSRL 0x00000000
552 #define CFG_GPIO0_TCR 0xF7FF8014
555 * Internal Definitions
559 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
560 #define BOOTFLAG_WARM 0x02 /* Software reboot */
562 #if 1 /* test-only */
563 #define CONFIG_NO_SERIAL_EEPROM
564 /*#undef CONFIG_NO_SERIAL_EEPROM*/
565 /*----------------------------------------------------------------------------*/
566 /*----------------------------------------------------------------------------*/
567 /*----------------------------------------------------------------------------*/
568 #ifdef CONFIG_NO_SERIAL_EEPROM
572 !-------------------------------------------------------------------------------
573 ! Defines for entry options.
574 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
575 ! are plugged in the board will be utilized as non-ECC DIMMs.
576 !-------------------------------------------------------------------------------
578 #undef AUTO_MEMORY_CONFIG
579 #define DIMM_READ_ADDR 0xAB
580 #define DIMM_WRITE_ADDR 0xAA
583 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
584 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
585 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
586 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
587 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
588 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
589 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
590 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
591 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
592 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
594 /* Defines for CPC0_PLLMR1 Register fields */
595 #define PLL_ACTIVE 0x80000000
596 #define CPC0_PLLMR1_SSCS 0x80000000
597 #define PLL_RESET 0x40000000
598 #define CPC0_PLLMR1_PLLR 0x40000000
599 /* Feedback multiplier */
600 #define PLL_FBKDIV 0x00F00000
601 #define CPC0_PLLMR1_FBDV 0x00F00000
602 #define PLL_FBKDIV_16 0x00000000
603 #define PLL_FBKDIV_1 0x00100000
604 #define PLL_FBKDIV_2 0x00200000
605 #define PLL_FBKDIV_3 0x00300000
606 #define PLL_FBKDIV_4 0x00400000
607 #define PLL_FBKDIV_5 0x00500000
608 #define PLL_FBKDIV_6 0x00600000
609 #define PLL_FBKDIV_7 0x00700000
610 #define PLL_FBKDIV_8 0x00800000
611 #define PLL_FBKDIV_9 0x00900000
612 #define PLL_FBKDIV_10 0x00A00000
613 #define PLL_FBKDIV_11 0x00B00000
614 #define PLL_FBKDIV_12 0x00C00000
615 #define PLL_FBKDIV_13 0x00D00000
616 #define PLL_FBKDIV_14 0x00E00000
617 #define PLL_FBKDIV_15 0x00F00000
618 /* Forward A divisor */
619 #define PLL_FWDDIVA 0x00070000
620 #define CPC0_PLLMR1_FWDVA 0x00070000
621 #define PLL_FWDDIVA_8 0x00000000
622 #define PLL_FWDDIVA_7 0x00010000
623 #define PLL_FWDDIVA_6 0x00020000
624 #define PLL_FWDDIVA_5 0x00030000
625 #define PLL_FWDDIVA_4 0x00040000
626 #define PLL_FWDDIVA_3 0x00050000
627 #define PLL_FWDDIVA_2 0x00060000
628 #define PLL_FWDDIVA_1 0x00070000
629 /* Forward B divisor */
630 #define PLL_FWDDIVB 0x00007000
631 #define CPC0_PLLMR1_FWDVB 0x00007000
632 #define PLL_FWDDIVB_8 0x00000000
633 #define PLL_FWDDIVB_7 0x00001000
634 #define PLL_FWDDIVB_6 0x00002000
635 #define PLL_FWDDIVB_5 0x00003000
636 #define PLL_FWDDIVB_4 0x00004000
637 #define PLL_FWDDIVB_3 0x00005000
638 #define PLL_FWDDIVB_2 0x00006000
639 #define PLL_FWDDIVB_1 0x00007000
641 #define PLL_TUNE_MASK 0x000003FF
642 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
643 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
644 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
645 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
646 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
647 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
648 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
650 /* Defines for CPC0_PLLMR0 Register fields */
652 #define PLL_CPUDIV 0x00300000
653 #define CPC0_PLLMR0_CCDV 0x00300000
654 #define PLL_CPUDIV_1 0x00000000
655 #define PLL_CPUDIV_2 0x00100000
656 #define PLL_CPUDIV_3 0x00200000
657 #define PLL_CPUDIV_4 0x00300000
659 #define PLL_PLBDIV 0x00030000
660 #define CPC0_PLLMR0_CBDV 0x00030000
661 #define PLL_PLBDIV_1 0x00000000
662 #define PLL_PLBDIV_2 0x00010000
663 #define PLL_PLBDIV_3 0x00020000
664 #define PLL_PLBDIV_4 0x00030000
666 #define PLL_OPBDIV 0x00003000
667 #define CPC0_PLLMR0_OPDV 0x00003000
668 #define PLL_OPBDIV_1 0x00000000
669 #define PLL_OPBDIV_2 0x00001000
670 #define PLL_OPBDIV_3 0x00002000
671 #define PLL_OPBDIV_4 0x00003000
673 #define PLL_EXTBUSDIV 0x00000300
674 #define CPC0_PLLMR0_EPDV 0x00000300
675 #define PLL_EXTBUSDIV_2 0x00000000
676 #define PLL_EXTBUSDIV_3 0x00000100
677 #define PLL_EXTBUSDIV_4 0x00000200
678 #define PLL_EXTBUSDIV_5 0x00000300
680 #define PLL_MALDIV 0x00000030
681 #define CPC0_PLLMR0_MPDV 0x00000030
682 #define PLL_MALDIV_1 0x00000000
683 #define PLL_MALDIV_2 0x00000010
684 #define PLL_MALDIV_3 0x00000020
685 #define PLL_MALDIV_4 0x00000030
687 #define PLL_PCIDIV 0x00000003
688 #define CPC0_PLLMR0_PPFD 0x00000003
689 #define PLL_PCIDIV_1 0x00000000
690 #define PLL_PCIDIV_2 0x00000001
691 #define PLL_PCIDIV_3 0x00000002
692 #define PLL_PCIDIV_4 0x00000003
695 !-------------------------------------------------------------------------------
696 ! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
697 ! assuming a 33.3MHz input clock to the 405EP.
698 !-------------------------------------------------------------------------------
700 #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
701 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
702 PLL_MALDIV_1 | PLL_PCIDIV_4)
703 #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
704 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
705 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
706 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
707 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
708 PLL_MALDIV_1 | PLL_PCIDIV_4)
709 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
710 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
711 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
712 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
713 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
714 PLL_MALDIV_1 | PLL_PCIDIV_4)
715 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
716 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
717 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
718 #if 0 /* test-only */
719 #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
720 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
722 #if 0 /* test-only */
723 #define PLLMR0_DEFAULT PLLMR0_200_100_50_33
724 #define PLLMR1_DEFAULT PLLMR1_200_100_50_33
726 #if 1 /* test-only */
727 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33
728 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33
734 #endif /* __CONFIG_H */