3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * board/config.h - configuration options, board specific
29 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
30 * U-BOOT port on RPXlite board
34 * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
35 * U-BOOT port on RPXlite DW version board--RPXlite_DW
43 * High Level Configuration Options
48 /* #ifdef DEPLOYMENT 1 */
51 #define CONFIG_MPC823 1 /* This is a MPC823e CPU. */
52 #define CONFIG_RPXLITE 1 /* RPXlite DW version board */
54 #ifdef CONFIG_LCD /* with LCD controller ? */
55 #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
58 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
59 #undef CONFIG_8xx_CONS_SMC2
60 #undef CONFIG_8xx_CONS_NONE
61 #define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */
64 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
66 #define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */
69 #define CONFIG_BOOT_RETRY_TIME -1
70 #define CONFIG_AUTOBOOT_KEYED
71 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds (stop with 'st')...\n"
72 #define CONFIG_AUTOBOOT_STOP_STR "st"
73 #define CONFIG_ZERO_BOOTDELAY_CHECK
74 #define CONFIG_RESET_TO_RETRY 1
75 #define CONFIG_BOOT_RETRY_MIN 1
76 #endif /* DEPLOYMENT */
79 /* pre-boot commands */
80 #define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial"
82 #undef CONFIG_BOOTARGS
83 #define CONFIG_EXTRA_ENV_SETTINGS \
85 "nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \
86 "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
87 "ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \
88 "addip=setenv bootargs $(bootargs) " \
89 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
90 ":$(hostname):$(netdev):off panic=1\0" \
91 "flash_nfs=run nfsargs addip;" \
92 "bootm $(kernel_addr)\0" \
93 "flash_self=run ramargs addip;" \
94 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
95 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
96 "gatewayip=172.16.115.254\0" \
97 "netmask=255.255.255.0\0" \
98 "kernel_addr=ff040000\0" \
99 "ramdisk_addr=ff200000\0" \
100 "ku=era $(kernel_addr) ff1fffff;cp.b 100000 $(kernel_addr) " \
101 "$(filesize);md $(kernel_addr);" \
102 "echo kernel updating finished\0" \
103 "uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \
104 "$(filesize);md ff000000;" \
105 "echo u-boot updating finished\0" \
106 "eu=protect off 1:6;era 1:6;reset\0" \
107 "lcd=setenv stdout lcd;setenv stdin lcd\0" \
108 "ser=setenv stdout serial;setenv stdin serial\0" \
111 #define CONFIG_BOOTCOMMAND "run flash_self"
113 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
114 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
115 #undef CONFIG_WATCHDOG /* watchdog disabled */
116 #undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */
118 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
120 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
121 #include <cmd_confdefs.h>
124 * Miscellaneous configurable options
126 #define CFG_LONGHELP /* undef to save memory */
127 #define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */
129 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
130 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
132 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
135 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
136 #define CFG_MAXARGS 16 /* max number of command args */
137 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
139 #define CFG_MEMTEST_START 0x0040000 /* memtest works on */
140 #define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
141 #define CFG_LOAD_ADDR 0x100000 /* default load address */
143 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
144 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
147 * Low Level Configuration Settings
148 * (address mappings, register initial values, etc.)
149 * You should know what you are doing if you make changes here.
151 /*-----------------------------------------------------------------------
152 * Internal Memory Mapped Register
154 #define CFG_IMMR 0xFA200000
156 /*-----------------------------------------------------------------------
157 * Definitions for initial stack pointer and data area (in DPRAM)
159 #define CFG_INIT_RAM_ADDR CFG_IMMR
160 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
161 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
162 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
163 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
165 /*-----------------------------------------------------------------------
166 * Start addresses for the final memory configuration
167 * (Set up by the startup code)
168 * Please note that CFG_SDRAM_BASE _must_ start at 0
170 #define CFG_SDRAM_BASE 0x00000000
171 #define CFG_FLASH_BASE 0xFF000000
173 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
174 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
176 #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
179 #define CFG_MONITOR_BASE 0xFF000000
180 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
187 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
189 /*-----------------------------------------------------------------------
192 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
193 #define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
194 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
195 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
197 #ifdef CFG_ENV_IS_IN_NVRAM
198 #define CFG_ENV_ADDR 0xFA000100
199 #define CFG_ENV_SIZE 0x1000
201 #define CFG_ENV_IS_IN_FLASH
202 #define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
203 #define CFG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
204 #endif /* CFG_ENV_IS_IN_NVRAM */
206 #define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
208 /*-----------------------------------------------------------------------
209 * Cache Configuration
211 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
212 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
213 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
216 /*-----------------------------------------------------------------------
217 * SYPCR - System Protection Control 32-bit 12-35
218 * SYPCR can only be written once after reset!
219 *-----------------------------------------------------------------------
220 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
222 #if defined(CONFIG_WATCHDOG)
223 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
224 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
226 #define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
227 #endif /* We can get SYPCR: 0xFFFF0689. */
229 /*-----------------------------------------------------------------------
230 * SIUMCR - SIU Module Configuration 32-bit 12-30
231 *-----------------------------------------------------------------------
232 * PCMCIA config., multi-function pin tri-state
234 #define CFG_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */
236 /*---------------------------------------------------------------------
237 * TBSCR - Time Base Status and Control 16-bit 12-16
238 *---------------------------------------------------------------------
239 * Clear Reference Interrupt Status, Timebase freezing enabled
241 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
242 /* TBSCR: 0x00C3 [SAM] */
244 /*-----------------------------------------------------------------------
245 * RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18
246 *-----------------------------------------------------------------------
247 * [RTC enabled but not stopped on FRZ]
249 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */
251 /*-----------------------------------------------------------------------
252 * PISCR - Periodic Interrupt Status and Control 16-bit 12-23
253 *-----------------------------------------------------------------------
254 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
255 * [Periodic timer enabled,Periodic timer interrupt disable. ]
257 #define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */
259 /*-----------------------------------------------------------------------
260 * PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7
261 *-----------------------------------------------------------------------
262 * Reset PLL lock status sticky bit, timer expired status bit and timer
263 * interrupt status bit
265 /* up to 64 MHz we use a 1:2 clock */
266 #if defined(RPXlite_64MHz)
267 #define CFG_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */
269 #define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
272 /*-----------------------------------------------------------------------
273 * SCCR - System Clock and reset Control Register 5-3
274 *-----------------------------------------------------------------------
275 * Set clock output, timebase and RTC source and divider,
276 * power management and some other internal clocks
278 #define SCCR_MASK SCCR_EBDF00
279 /* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
280 #if defined(RPXlite_64MHz)
281 #define CFG_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */
283 #define CFG_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */
286 /*-----------------------------------------------------------------------
288 *-----------------------------------------------------------------------
290 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
291 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
292 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
293 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
294 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
295 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
296 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
297 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
299 /*-----------------------------------------------------------------------
300 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
301 *-----------------------------------------------------------------------
303 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
305 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
306 #undef CONFIG_IDE_LED /* LED for ide not supported */
307 #undef CONFIG_IDE_RESET /* reset for ide not supported */
309 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
310 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
312 #define CFG_ATA_IDE0_OFFSET 0x0000
313 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
315 /* Offset for data I/O */
316 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
318 /* Offset for normal register accesses */
319 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
321 /* Offset for alternate registers */
322 #define CFG_ATA_ALT_OFFSET 0x0100
327 * Init Memory Controller:
329 * BR0 and OR0 (FLASH)
331 #define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */
332 #define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask */
334 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
335 #define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
336 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
337 #define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
340 * BR1 and OR1 (SDRAM)
343 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
344 #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */
346 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
347 #define CFG_OR_TIMING_SDRAM 0x00000E00
348 #define CFG_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK))
349 #define CFG_OR1_PRELIM ( CFG_OR_AM_SDRAM | CFG_OR_TIMING_SDRAM )
350 #define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
352 /* RPXlite mem setting */
353 #define CFG_BR3_PRELIM 0xFA400001 /* BCSR */
354 #define CFG_OR3_PRELIM 0xFF7F8900
355 #define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
356 #define CFG_OR4_PRELIM 0xFFFE0040
359 * Memory Periodic Timer Prescaler
361 /* periodic timer for refresh */
362 #if defined(RPXlite_64MHz)
363 #define CFG_MAMR_PTA 32
365 #define CFG_MAMR_PTA 20
369 * Refresh clock Prescalar
371 #define CFG_MPTPR MPTPR_PTP_DIV2
374 * MAMR settings for SDRAM
378 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
379 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
380 /* CFG_MAMR_9COL:0x20904000 @ 64MHz */
383 * Internal Definitions
387 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
388 #define BOOTFLAG_WARM 0x02 /* Software reboot */
390 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
391 /* Configuration variable added by yooth. */
392 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
396 * Board Status and Control Registers
399 #define BCSR0 0xFA400000
400 #define BCSR1 0xFA400001
401 #define BCSR2 0xFA400002
402 #define BCSR3 0xFA400003
404 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
405 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
406 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
407 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
408 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
409 #define BCSR0_COLTEST 0x20
410 #define BCSR0_ETHLPBK 0x40
411 #define BCSR0_ETHEN 0x80
413 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
414 #define BCSR1_PCVCTL6 0x02
415 #define BCSR1_PCVCTL5 0x04
416 #define BCSR1_PCVCTL4 0x08
417 #define BCSR1_IPB5SEL 0x10
419 #define BCSR1_SMC1CTS 0x40 /* Added by SAM. */
420 #define BCSR1_SMC1TRS 0x80 /* Added by SAM. */
422 #define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */
423 #define BCSR2_ENBRG1 0x04 /* Added by SAM. */
425 #define BCSR2_ENPA5HDR 0x08 /* USB Control */
426 #define BCSR2_ENUSBCLK 0x10
427 #define BCSR2_USBPWREN 0x20
428 #define BCSR2_USBSPD 0x40
429 #define BCSR2_USBSUSP 0x80
431 #define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */
432 #define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */
433 #define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */
434 #define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */
436 #define BCSR3_D27 0x10 /* Dip Switch settings */
437 #define BCSR3_D26 0x20
438 #define BCSR3_D25 0x40
439 #define BCSR3_D24 0x80
442 * Environment setting
444 #define CONFIG_ETHADDR 00:10:EC:00:37:5B
445 #define CONFIG_IPADDR 172.16.115.7
446 #define CONFIG_SERVERIP 172.16.115.6
447 #define CONFIG_ROOTPATH /workspace/myfilesystem/target/
448 #define CONFIG_BOOTFILE uImage.rpxusb
450 #endif /* __CONFIG_H */