2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * U-Boot configuration for Analogue&Micro Rattler boards.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #define CPU_ID_STR "MPC8248"
32 #define CONFIG_MPC8260
33 #define CPU_ID_STR "MPC8250"
34 #endif /* CONFIG_MPC8248 */
36 #define CONFIG_RATTLER /* Analogue&Micro Rattler board */
40 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
41 #define CONFIG_ENV_OVERWRITE
44 * Select serial console configuration
46 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
47 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
50 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
51 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
52 #undef CONFIG_CONS_NONE /* It's not on external UART */
53 #define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
56 * Select ethernet configuration
58 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
59 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
62 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
63 * must be defined elsewhere (as for the console), or CFG_CMD_NET must
64 * be removed from CONFIG_COMMANDS to remove support for networking.
66 #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
67 #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
68 #undef CONFIG_ETHER_NONE /* No external Ethernet */
70 #ifdef CONFIG_ETHER_ON_FCC
72 #define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
74 #if (CONFIG_ETHER_INDEX == 1)
76 /* - Rx clock is CLK11
78 * - BDs/buffers on 60x bus
81 #define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
82 #define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
83 #define CFG_CPMFCR_RAMTYPE 0
84 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
86 #elif (CONFIG_ETHER_INDEX == 2)
88 /* - Rx clock is CLK15
90 * - BDs/buffers on 60x bus
93 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
94 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
95 #define CFG_CPMFCR_RAMTYPE 0
96 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
98 #endif /* CONFIG_ETHER_INDEX */
100 #define CONFIG_MII /* MII PHY management */
101 #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
103 * GPIO pins used for bit-banged MII communications
105 #define MDIO_PORT 2 /* Port C */
106 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
107 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
108 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
110 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
111 else iop->pdat &= ~0x00400000
113 #define MDC(bit) if(bit) iop->pdat |= 0x00800000; \
114 else iop->pdat &= ~0x00800000
116 #define MIIDELAY udelay(1)
118 #endif /* CONFIG_ETHER_ON_FCC */
120 #ifndef CONFIG_8260_CLKIN
121 #define CONFIG_8260_CLKIN 100000000 /* in Hz */
124 #define CONFIG_BAUDRATE 38400
126 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
135 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
136 #include <cmd_confdefs.h>
138 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
139 #define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
140 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
142 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
143 #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
144 #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
145 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
146 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
147 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
150 #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
151 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
154 * Miscellaneous configurable options
156 #define CFG_HUSH_PARSER
157 #define CFG_PROMPT_HUSH_PS2 "> "
158 #define CFG_LONGHELP /* undef to save memory */
159 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
160 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
161 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
163 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
165 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
166 #define CFG_MAXARGS 16 /* max number of command args */
167 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
169 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
170 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
172 #define CFG_LOAD_ADDR 0x100000 /* default load address */
174 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
176 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
178 #define CFG_FLASH_BASE 0xFE000000
179 #define CFG_FLASH_CFI
180 #define CFG_FLASH_CFI_DRIVER
181 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
182 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
184 #define CFG_DIRECT_FLASH_TFTP
186 #if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
187 #define CFG_JFFS2_FIRST_BANK 0
188 #define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
189 #define CFG_JFFS2_FIRST_SECTOR 16
190 #define CFG_JFFS2_SORT_FRAGMENTS
191 #endif /* CFG_CMD_JFFS2 */
193 #define CFG_MONITOR_BASE TEXT_BASE
194 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
198 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
200 #define CFG_ENV_IS_IN_FLASH
202 #ifdef CFG_ENV_IS_IN_FLASH
203 #define CFG_ENV_SECT_SIZE 0x10000
204 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
205 #endif /* CFG_ENV_IS_IN_FLASH */
207 #define CFG_DEFAULT_IMMR 0xFF010000
209 #define CFG_IMMR 0xF0000000
211 #define CFG_INIT_RAM_ADDR CFG_IMMR
212 #define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
213 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
214 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
215 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
217 #define CFG_SDRAM_BASE 0x00000000
218 #define CFG_SDRAM_SIZE 32
219 #define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041)
220 #define CFG_SDRAM_OR 0xFE002EC0
222 #define CFG_BCSR 0xFC000000
224 /* Hard reset configuration word */
225 #define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
227 #define CFG_HRCW_SLAVE1 0
228 #define CFG_HRCW_SLAVE2 0
229 #define CFG_HRCW_SLAVE3 0
230 #define CFG_HRCW_SLAVE4 0
231 #define CFG_HRCW_SLAVE5 0
232 #define CFG_HRCW_SLAVE6 0
233 #define CFG_HRCW_SLAVE7 0
235 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
236 #define BOOTFLAG_WARM 0x02 /* Software reboot */
238 #define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
239 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
241 #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
242 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
243 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
246 #define CFG_HID0_INIT 0
247 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
251 #define CFG_SIUMCR 0x0E04C000
252 #define CFG_SYPCR 0xFFFFFFC3
253 #define CFG_BCR 0x00000000
254 #define CFG_SCCR SCCR_DFBRG01
256 #define CFG_RMR RMR_CSRE
257 #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
258 #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
261 #define CFG_PSDMR 0x8249A452
262 #define CFG_PSRT 0x1F
263 #define CFG_MPTPR 0x2000
265 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001001)
266 #define CFG_OR0_PRELIM 0xFF001ED6
267 #define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801)
268 #define CFG_OR7_PRELIM 0xFFFF87F6
270 #define CFG_RESET_ADDRESS 0xC0000000
272 #endif /* __CONFIG_H */