2 * Copyright (C) Sheldon Instruments, Inc. 2008
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * simpc8313 board configuration file
30 * High Level Configuration Options
32 #define CONFIG_NAND_U_BOOT
35 #define CONFIG_MPC83xx 1
36 #define CONFIG_MPC831x 1
37 #define CONFIG_MPC8313 1
40 #define CONFIG_FSL_ELBC 1
42 #define CONFIG_MISC_INIT_R
47 * TSEC1 is Marvell PHY 88E1118
50 #define CONFIG_SYS_33MHZ
52 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
54 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
56 #define CONFIG_SYS_IMMR 0xE0000000
58 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
59 #define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
62 #define CONFIG_SYS_MEMTEST_START 0x00001000
63 #define CONFIG_SYS_MEMTEST_END 0x07f00000
65 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
66 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
69 * Device configurations
76 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
78 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
80 #define CONFIG_VERY_BIG_RAM
81 #define CONFIG_MAX_MEM_MAPPED (512 << 20)
83 #define CONFIG_SYS_DDRCDR ( DDRCDR_EN \
87 /* 0x73000002 TODO ODR & DRN ? */
90 * FLASH on the Local Bus
92 #define CONFIG_SYS_NO_FLASH
94 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
96 #if !defined(CONFIG_NAND_SPL)
97 #define CONFIG_SYS_RAMBOOT
100 #define CONFIG_SYS_INIT_RAM_LOCK 1
101 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
102 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
104 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
105 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
106 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
108 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
109 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
110 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
113 * Local Bus LCRR and LBCR regs
115 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
116 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
117 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
118 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
119 | (0xFF << LBCR_BMT_SHIFT) \
120 | 0xF ) /* 0x0004ff0f */
122 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
124 /* drivers/mtd/nand/nand.c */
125 #ifdef CONFIG_NAND_SPL
126 #define CONFIG_SYS_NAND_BASE 0xFFF00000
128 #define CONFIG_SYS_NAND_BASE 0xE2800000
130 #define CONFIG_SYS_FPGA_BASE 0xFF000000
132 #define CONFIG_SYS_MAX_NAND_DEVICE 1
133 #define NAND_MAX_CHIPS 1
134 #define CONFIG_MTD_NAND_VERIFY_WRITE
135 #define CONFIG_CMD_NAND 1
136 #define CONFIG_NAND_FSL_ELBC 1
138 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
139 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
140 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
141 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
142 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
144 #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
145 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
146 | BR_PS_8 /* Port Size = 8 bit */ \
147 | BR_MS_FCM /* MSEL = FCM */ \
150 #ifdef CONFIG_NAND_SP
151 #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
158 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
159 #define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
160 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
161 #define NAND_CACHE_PAGES 32
162 #elif defined(CONFIG_NAND_LP)
163 #define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \
171 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
172 #define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
173 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
174 #define NAND_CACHE_PAGES 64
176 #error Page size of NAND not defined.
177 #endif /* CONFIG_NAND_SP */
179 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
181 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
182 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
184 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
186 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
187 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
189 #define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \
193 #define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \
196 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
197 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB)
200 * JFFS2 configuration
202 #define CONFIG_JFFS2_NAND
203 #define CONFIG_JFFS2_DEV "nand0"
205 /* mtdparts command line support */
206 #define CONFIG_CMD_MTDPARTS
207 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
208 #define MTDIDS_DEFAULT "nand0=nand0"
209 #define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
211 /* pass open firmware flat tree */
212 #define CONFIG_OF_LIBFDT 1
213 #define CONFIG_OF_BOARD_SETUP 1
214 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
219 #define CONFIG_CONS_INDEX 1
220 #define CONFIG_SYS_NS16550
221 #define CONFIG_SYS_NS16550_SERIAL
222 #define CONFIG_SYS_NS16550_REG_SIZE 1
223 #ifdef CONFIG_NAND_SPL
224 #define CONFIG_NS16550_MIN_FUNCTIONS
227 #define CONFIG_SYS_BAUDRATE_TABLE \
228 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
230 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
231 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
233 /* Use the HUSH parser */
234 #define CONFIG_SYS_HUSH_PARSER
235 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
238 #define CONFIG_HARD_I2C /* I2C with hardware support*/
239 #define CONFIG_FSL_I2C
240 #define CONFIG_I2C_MULTI_BUS
241 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
242 #define CONFIG_SYS_I2C_SLAVE 0x7F
243 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
244 #define CONFIG_SYS_I2C_OFFSET 0x3000
245 #define CONFIG_SYS_I2C2_OFFSET 0x3100
249 * Addresses are mapped 1-1.
251 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
252 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
253 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
254 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
255 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
256 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
257 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
258 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
259 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
261 #define CONFIG_PCI_PNP /* do pci plug-and-play */
262 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
267 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
269 #define CONFIG_NET_MULTI
270 #define CONFIG_GMII /* MII PHY management */
273 #define CONFIG_HAS_ETH0
274 #define CONFIG_TSEC1_NAME "TSEC0"
275 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
276 #define TSEC1_PHY_ADDR 0x0
277 #define TSEC1_FLAGS TSEC_GIGABIT
278 #define TSEC1_PHYIDX 0
282 #define CONFIG_HAS_ETH1
283 #define CONFIG_TSEC2_NAME "TSEC1"
284 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
285 #define TSEC2_PHY_ADDR 4
286 #define TSEC2_FLAGS TSEC_GIGABIT
287 #define TSEC2_PHYIDX 0
291 /* Options are: TSEC[0-1] */
292 #define CONFIG_ETHPRIME "TSEC1"
295 * Configure on-board RTC
297 #define CONFIG_RTC_DS1337
298 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
303 #if defined(CONFIG_NAND_U_BOOT)
304 #define CONFIG_ENV_IS_IN_NAND 1
305 #define CONFIG_ENV_OFFSET (768 * 1024)
306 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
307 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
308 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
309 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
310 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
311 #elif !defined(CONFIG_SYS_RAMBOOT)
312 #define CONFIG_ENV_IS_IN_FLASH 1
313 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
314 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
315 #define CONFIG_ENV_SIZE 0x2000
317 /* Address and size of Redundant Environment Sector */
319 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
320 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
321 #define CONFIG_ENV_SIZE 0x2000
324 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
325 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
330 #define CONFIG_BOOTP_BOOTFILESIZE
331 #define CONFIG_BOOTP_BOOTPATH
332 #define CONFIG_BOOTP_GATEWAY
333 #define CONFIG_BOOTP_HOSTNAME
337 * Command line configuration.
339 #include <config_cmd_default.h>
340 #undef CONFIG_CMD_IMLS
341 #undef CONFIG_CMD_FLASH
343 #define CONFIG_CMD_PING
344 #define CONFIG_CMD_DHCP
345 #define CONFIG_CMD_I2C
346 #define CONFIG_CMD_MII
347 #define CONFIG_CMD_DATE
348 #define CONFIG_CMD_PCI
349 #define CONFIG_CMD_JFFS2
351 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
352 #undef CONFIG_CMD_SAVEENV
353 #undef CONFIG_CMD_LOADS
356 #define CONFIG_CMDLINE_EDITING 1
357 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
360 * Miscellaneous configurable options
362 #define CONFIG_SYS_LONGHELP /* undef to save memory */
363 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
364 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
365 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
367 #define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \
368 + sizeof(CONFIG_SYS_PROMPT) \
369 + 16 ) /* Print Buffer Size */
370 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
371 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
372 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
375 * For booting Linux, the board info and command line data
376 * have to be in the first 8 MB of memory, since this is
377 * the maximum mapped by the Linux kernel during initialization.
379 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
381 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
383 #define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
384 | 0x20000000 /* reserved */ \
385 | HRCWL_DDR_TO_SCB_CLK_2X1 \
386 | HRCWL_CSB_TO_CLKIN_4X1 \
387 | HRCWL_CORE_TO_CSB_2_5X1 )
389 #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
391 #define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \
392 | HRCWH_PCI1_ARBITER_ENABLE \
393 | HRCWH_CORE_ENABLE \
394 | HRCWH_BOOTSEQ_DISABLE \
395 | HRCWH_SW_WATCHDOG_DISABLE \
396 | HRCWH_TSEC1M_IN_RGMII \
397 | HRCWH_TSEC2M_IN_RGMII \
399 | HRCWH_LALE_NORMAL )
401 #ifdef CONFIG_NAND_LP
402 #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
403 | HRCWH_FROM_0XFFF00100 \
404 | HRCWH_ROM_LOC_NAND_LP_8BIT \
407 #define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
408 | HRCWH_FROM_0XFFF00100 \
409 | HRCWH_ROM_LOC_NAND_SP_8BIT \
410 | HRCWH_RL_EXT_NAND )
413 /* System IO Config */
414 #define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \
422 #define CONFIG_SYS_SICRL ( SICRL_LBC \
426 #define CONFIG_SYS_HID0_INIT 0x000000000
427 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
428 HID0_ENABLE_INSTRUCTION_CACHE | \
429 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
431 #define CONFIG_SYS_HID2 HID2_HBE
433 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
435 /* DDR @ 0x00000000 */
436 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
437 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
438 #define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
439 #define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
441 /* PCI @ 0x80000000 */
442 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
443 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
444 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
445 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
447 /* PCI2 not supported on 8313 */
448 #define CONFIG_SYS_IBAT4L (0)
449 #define CONFIG_SYS_IBAT4U (0)
451 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
452 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
453 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
455 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
456 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
457 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
459 #define CONFIG_SYS_IBAT7L (0)
460 #define CONFIG_SYS_IBAT7U (0)
462 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
463 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
464 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
465 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
466 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
467 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
468 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
469 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
470 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
471 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
472 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
473 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
474 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
475 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
476 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
477 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
480 * Internal Definitions
484 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
485 #define BOOTFLAG_WARM 0x02 /* Software reboot */
488 * Environment Configuration
490 #define CONFIG_ENV_OVERWRITE
492 #define CONFIG_NETDEV eth1
494 #define CONFIG_HOSTNAME simpc8313
495 #define CONFIG_ROOTPATH /tftpboot/
496 #define CONFIG_BOOTFILE /tftpboot/uImage
497 #define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */
498 #define CONFIG_FDTFILE simpc8313.dtb
500 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
501 #define CONFIG_BOOTDELAY 5 /* 5 second delay */
502 #define CONFIG_BAUDRATE 115200
504 #define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
506 #define XMK_STR(x) #x
507 #define MK_STR(x) XMK_STR(x)
509 #define CONFIG_EXTRA_ENV_SETTINGS \
510 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
512 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
513 "tftpflash=tftpboot $loadaddr $uboot; " \
514 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
515 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
516 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
517 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
518 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
520 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
522 "setbootargs=setenv bootargs " \
523 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
524 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
525 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
526 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
527 "load_uboot=tftp 100000 u-boot-nand.bin\0" \
528 "burn_uboot=nand erase u-boot 80000; " \
529 "nand write 100000 u-boot $filesize\0" \
530 "update_uboot=run load_uboot;run burn_uboot\0" \
531 "mtdids=nand0=nand0\0" \
532 "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
533 "nfsargs=setenv bootargs root=/dev/nfs rw " \
534 "nfsroot=${serverip}:${rootpath}\0" \
535 "ramargs=setenv bootargs root=/dev/ram rw\0" \
536 "addip=setenv bootargs ${bootargs} " \
537 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
538 ":${hostname}:${netdev}:off panic=1\0" \
539 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
540 "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
541 "console=ttyS0,115200\0" \
544 #define CONFIG_NFSBOOTCOMMAND \
545 "setenv rootdev /dev/nfs;" \
548 "tftp $loadaddr $bootfile;" \
549 "tftp $fdtaddr $fdtfile;" \
550 "bootm $loadaddr - $fdtaddr"
552 #define CONFIG_RAMBOOTCOMMAND \
553 "setenv rootdev /dev/ram;" \
555 "tftp $ramdiskaddr $ramdiskfile;" \
556 "tftp $loadaddr $bootfile;" \
557 "tftp $fdtaddr $fdtfile;" \
558 "bootm $loadaddr $ramdiskaddr $fdtaddr"
563 #endif /* __CONFIG_H */