2 * (C) Copyright 2001 - 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* ------------------------------------------------------------------------- */
26 * Configuration settings for the SL8245 board.
29 /* ------------------------------------------------------------------------- */
32 * board/config.h - configuration options, board specific
39 * High Level Configuration Options
43 #define CONFIG_MPC824X 1
44 #define CONFIG_MPC8245 1
45 #define CONFIG_SL8245 1
48 #define CONFIG_CONS_INDEX 1
49 #define CONFIG_BAUDRATE 115200
50 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
52 #define CONFIG_BOOTDELAY 5
54 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI)
56 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
58 #include <cmd_confdefs.h>
62 * Miscellaneous configurable options
64 #undef CFG_LONGHELP /* undef to save memory */
65 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
66 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
70 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
71 #define CFG_MAXARGS 8 /* Max number of command args */
72 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
73 #define CFG_LOAD_ADDR 0x00400000 /* Default load address */
75 /*-----------------------------------------------------------------------
76 * Start addresses for the final memory configuration
77 * (Set up by the startup code)
78 * Please note that CFG_SDRAM_BASE _must_ start at 0
80 #define CFG_SDRAM_BASE 0x00000000
82 #define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */
83 #define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM
84 #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM }
86 #define CFG_RESET_ADDRESS 0xFFF00100
88 #define CFG_EUMB_ADDR 0xFC000000
90 #define CFG_MONITOR_BASE TEXT_BASE
91 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
92 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
94 #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
95 #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
97 /* Maximum amount of RAM.
99 #define CFG_MAX_RAM_SIZE 0x10000000 /* 0 .. 256 MB of (S)DRAM */
102 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
109 * NS16550 Configuration
112 #define CFG_NS16550_SERIAL
114 #define CFG_NS16550_REG_SIZE 1
116 #define CFG_NS16550_CLK get_bus_freq(0)
118 #define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
120 /*-----------------------------------------------------------------------
121 * Definitions for initial stack pointer and data area
124 #define CFG_GBL_DATA_SIZE 128
125 #define CFG_INIT_RAM_ADDR 0x40000000
126 #define CFG_INIT_RAM_END 0x1000
127 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
130 * Low Level Configuration Settings
131 * (address mappings, register initial values, etc.)
132 * You should know what you are doing if you make changes here.
133 * For the detail description refer to the MPC8240 user's manual.
136 #define CONFIG_SYS_CLK_FREQ 66666666 /* external frequency to pll */
139 /* Bit-field values for MCCR1.
143 #define CFG_BANK0_ROW 2
145 /* Bit-field values for MCCR2.
147 #define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
149 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
151 #define CFG_BSTOPRE 192
153 /* Bit-field values for MCCR3.
155 #define CFG_REFREC 2 /* Refresh to activate interval */
157 /* Bit-field values for MCCR4.
159 #define CFG_PRETOACT 2 /* Precharge to activate interval */
160 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
161 #define CFG_ACTORW 3 /* FIXME was 2 */
162 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
163 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
164 #define CFG_REGISTERD_TYPE_BUFFER 1
166 #define CFG_REGDIMM 0
168 #define CFG_ODCR 0xff /* configures line driver impedances, */
169 /* see 8245 book for bit definitions */
170 #define CFG_PGMAX 0x32 /* how long the 8245 retains the */
171 /* currently accessed page in memory */
172 /* see 8245 book for details */
174 /* Memory bank settings.
175 * Only bits 20-29 are actually used from these vales to set the
176 * start/end addresses. The upper two bits will always be 0, and the lower
177 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
178 * address. Refer to the MPC8240 book.
181 #define CFG_BANK0_START 0x00000000
182 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
183 #define CFG_BANK0_ENABLE 1
184 #define CFG_BANK1_START 0x3ff00000
185 #define CFG_BANK1_END 0x3fffffff
186 #define CFG_BANK1_ENABLE 0
187 #define CFG_BANK2_START 0x3ff00000
188 #define CFG_BANK2_END 0x3fffffff
189 #define CFG_BANK2_ENABLE 0
190 #define CFG_BANK3_START 0x3ff00000
191 #define CFG_BANK3_END 0x3fffffff
192 #define CFG_BANK3_ENABLE 0
193 #define CFG_BANK4_START 0x3ff00000
194 #define CFG_BANK4_END 0x3fffffff
195 #define CFG_BANK4_ENABLE 0
196 #define CFG_BANK5_START 0x3ff00000
197 #define CFG_BANK5_END 0x3fffffff
198 #define CFG_BANK5_ENABLE 0
199 #define CFG_BANK6_START 0x3ff00000
200 #define CFG_BANK6_END 0x3fffffff
201 #define CFG_BANK6_ENABLE 0
202 #define CFG_BANK7_START 0x3ff00000
203 #define CFG_BANK7_END 0x3fffffff
204 #define CFG_BANK7_ENABLE 0
206 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
207 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
209 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
210 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
212 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
213 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
215 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
216 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
218 #define CFG_DBAT0L CFG_IBAT0L
219 #define CFG_DBAT0U CFG_IBAT0U
220 #define CFG_DBAT1L CFG_IBAT1L
221 #define CFG_DBAT1U CFG_IBAT1U
222 #define CFG_DBAT2L CFG_IBAT2L
223 #define CFG_DBAT2U CFG_IBAT2U
224 #define CFG_DBAT3L CFG_IBAT3L
225 #define CFG_DBAT3U CFG_IBAT3U
228 * For booting Linux, the board info and command line data
229 * have to be in the first 8 MB of memory, since this is
230 * the maximum mapped by the Linux kernel during initialization.
232 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
234 /*-----------------------------------------------------------------------
237 #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
238 #define CFG_MAX_FLASH_SECT 35 /* Max number of sectors per flash */
240 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
241 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
244 /* Warining: environment is not EMBEDDED in the U-Boot code.
245 * It's stored in flash separately.
247 #define CFG_ENV_IS_IN_FLASH 1
248 #define CFG_ENV_ADDR 0xFFFF0000
249 #define CFG_ENV_SIZE 0x00010000 /* Size of the Environment */
250 #define CFG_ENV_SECT_SIZE 0x00010000 /* Size of the Environment Sector */
252 /*-----------------------------------------------------------------------
253 * Cache Configuration
255 #define CFG_CACHELINE_SIZE 32
256 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
257 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
261 * Internal Definitions
265 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
266 #define BOOTFLAG_WARM 0x02 /* Software reboot */
268 /*-----------------------------------------------------------------------
270 *-----------------------------------------------------------------------
273 #define CONFIG_PCI_PNP
274 #undef CONFIG_PCI_SCAN_SHOW
278 #define CONFIG_NET_MULTI
281 #endif /* __CONFIG_H */