2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* ------------------------------------------------------------------------- */
27 * board/config.h - configuration options, board specific
34 * High Level Configuration Options
38 #define CONFIG_MPC824X 1
39 #define CONFIG_MPC8240 1
40 #define CONFIG_SANDPOINT 1
48 #define CONFIG_CONS_INDEX 1
49 #define CONFIG_BAUDRATE 9600
51 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
53 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
55 #define CONFIG_PREBOOT "echo;" \
56 "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
59 #undef CONFIG_BOOTARGS
61 #define CONFIG_EXTRA_ENV_SETTINGS \
63 "nfsargs=setenv bootargs root=/dev/nfs rw " \
64 "nfsroot=${serverip}:${rootpath}\0" \
65 "ramargs=setenv bootargs root=/dev/ram rw\0" \
66 "addip=setenv bootargs ${bootargs} " \
67 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
68 ":${hostname}:${netdev}:off panic=1\0" \
69 "net_self=tftp ${kernel_addr} ${bootfile};" \
70 "tftp ${ramdisk_addr} ${ramdisk};" \
71 "run ramargs addip;" \
72 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
73 "net_nfs=tftp ${kernel_addr} ${bootfile};" \
74 "run nfsargs addip;bootm\0" \
75 "rootpath=/opt/eldk/ppc_82xx\0" \
76 "bootfile=/tftpboot/SP8240/uImage\0" \
77 "ramdisk=/tftpboot/SP8240/uRamdisk\0" \
78 "kernel_addr=200000\0" \
79 "ramdisk_addr=400000\0" \
81 #define CONFIG_BOOTCOMMAND "run flash_self"
85 * Command line configuration.
87 #include <config_cmd_default.h>
89 #define CONFIG_CMD_DHCP
90 #define CONFIG_CMD_ELF
91 #define CONFIG_CMD_I2C
92 #define CONFIG_CMD_SDRAM
93 #define CONFIG_CMD_EEPROM
94 #define CONFIG_CMD_NFS
95 #define CONFIG_CMD_PCI
96 #define CONFIG_CMD_SNTP
99 #define CONFIG_DRAM_SPEED 100 /* MHz */
102 * Miscellaneous configurable options
104 #define CFG_LONGHELP 1 /* undef to save memory */
105 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
106 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
107 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
108 #define CFG_MAXARGS 16 /* max number of command args */
109 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
110 #define CFG_LOAD_ADDR 0x00100000 /* default load address */
111 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
113 /*-----------------------------------------------------------------------
115 *-----------------------------------------------------------------------
117 #define CONFIG_PCI /* include pci support */
118 #undef CONFIG_PCI_PNP
120 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
122 #define CONFIG_EEPRO100
123 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
125 #define PCI_ENET0_IOADDR 0x80000000
126 #define PCI_ENET0_MEMADDR 0x80000000
127 #define PCI_ENET1_IOADDR 0x81000000
128 #define PCI_ENET1_MEMADDR 0x81000000
131 /*-----------------------------------------------------------------------
132 * Start addresses for the final memory configuration
133 * (Set up by the startup code)
134 * Please note that CFG_SDRAM_BASE _must_ start at 0
136 #define CFG_SDRAM_BASE 0x00000000
137 #define CFG_MAX_RAM_SIZE 0x10000000
139 #define CFG_RESET_ADDRESS 0xFFF00100
141 #if defined (USE_DINK32)
142 #define CFG_MONITOR_LEN 0x00030000
143 #define CFG_MONITOR_BASE 0x00090000
144 #define CFG_RAMBOOT 1
145 #define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
146 #define CFG_INIT_RAM_END 0x10000
147 #define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
148 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
149 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
152 #define CFG_MONITOR_LEN 0x00030000
153 #define CFG_MONITOR_BASE TEXT_BASE
155 /*#define CFG_GBL_DATA_SIZE 256*/
156 #define CFG_GBL_DATA_SIZE 128
158 #define CFG_INIT_RAM_ADDR 0x40000000
159 #define CFG_INIT_RAM_END 0x1000
160 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
164 #define CFG_FLASH_BASE 0xFFF00000
166 #define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
168 #define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
170 #define CFG_ENV_IS_IN_FLASH 1
171 #define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
172 #define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
174 #define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
176 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
177 #define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
179 #define CFG_EUMB_ADDR 0xFC000000
181 #define CFG_ISA_MEM 0xFD000000
182 #define CFG_ISA_IO 0xFE000000
184 #define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
185 #define CFG_FLASH_RANGE_SIZE 0x01000000
186 #define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
187 #define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
190 * select i2c support configuration
192 * Supported configurations are {none, software, hardware} drivers.
193 * If the software driver is chosen, there are some additional
194 * configuration items that the driver uses to drive the port pins.
196 #define CONFIG_HARD_I2C 1 /* To enable I2C support */
197 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
198 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
199 #define CFG_I2C_SLAVE 0x7F
201 #ifdef CONFIG_SOFT_I2C
202 #error "Soft I2C is not configured properly. Please review!"
203 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
204 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
205 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
206 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
207 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
208 else iop->pdat &= ~0x00010000
209 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
210 else iop->pdat &= ~0x00020000
211 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
212 #endif /* CONFIG_SOFT_I2C */
215 #define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
216 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
217 #define CFG_EEPROM_PAGE_WRITE_BITS 3 /* write page size */
218 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
221 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
222 #define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
224 /*-----------------------------------------------------------------------
225 * Definitions for initial stack pointer and data area (in DPRAM)
229 #define CFG_WINBOND_83C553 1 /*has a winbond bridge */
230 #define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
231 #define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
232 #define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
234 #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
235 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
238 * NS87308 Configuration
240 #define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
242 #define CFG_NS87308_BADDR_10 1
244 #define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
245 CFG_NS87308_UART2 | \
246 CFG_NS87308_POWRMAN | \
247 CFG_NS87308_RTC_APC )
249 #undef CFG_NS87308_PS2MOD
251 #define CFG_NS87308_CS0_BASE 0x0076
252 #define CFG_NS87308_CS0_CONF 0x30
253 #define CFG_NS87308_CS1_BASE 0x0075
254 #define CFG_NS87308_CS1_CONF 0x30
255 #define CFG_NS87308_CS2_BASE 0x0074
256 #define CFG_NS87308_CS2_CONF 0x30
259 * NS16550 Configuration
262 #define CFG_NS16550_SERIAL
264 #define CFG_NS16550_REG_SIZE 1
266 #define CFG_NS16550_CLK 1843200
268 #define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
269 #define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
272 * Low Level Configuration Settings
273 * (address mappings, register initial values, etc.)
274 * You should know what you are doing if you make changes here.
277 #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
278 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1
280 #define CFG_ROMNAL 7 /*rom/flash next access time */
281 #define CFG_ROMFAL 11 /*rom/flash access time */
283 #define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
285 /* the following are for SDRAM only*/
286 #define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
287 #define CFG_REFREC 8 /* Refresh to activate interval */
288 #define CFG_RDLAT 4 /* data latency from read command */
289 #define CFG_PRETOACT 3 /* Precharge to activate interval */
290 #define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
291 #define CFG_ACTORW 3 /* Activate to R/W */
292 #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
293 #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
294 #define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
296 #define CFG_REGISTERD_TYPE_BUFFER 1
298 /* memory bank settings*/
300 * only bits 20-29 are actually used from these vales to set the
301 * start/end address the upper two bits will be 0, and the lower 20
302 * bits will be set to 0x00000 for a start address, or 0xfffff for an
305 #define CFG_BANK0_START 0x00000000
306 #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
307 #define CFG_BANK0_ENABLE 1
308 #define CFG_BANK1_START 0x3ff00000
309 #define CFG_BANK1_END 0x3fffffff
310 #define CFG_BANK1_ENABLE 0
311 #define CFG_BANK2_START 0x3ff00000
312 #define CFG_BANK2_END 0x3fffffff
313 #define CFG_BANK2_ENABLE 0
314 #define CFG_BANK3_START 0x3ff00000
315 #define CFG_BANK3_END 0x3fffffff
316 #define CFG_BANK3_ENABLE 0
317 #define CFG_BANK4_START 0x00000000
318 #define CFG_BANK4_END 0x00000000
319 #define CFG_BANK4_ENABLE 0
320 #define CFG_BANK5_START 0x00000000
321 #define CFG_BANK5_END 0x00000000
322 #define CFG_BANK5_ENABLE 0
323 #define CFG_BANK6_START 0x00000000
324 #define CFG_BANK6_END 0x00000000
325 #define CFG_BANK6_ENABLE 0
326 #define CFG_BANK7_START 0x00000000
327 #define CFG_BANK7_END 0x00000000
328 #define CFG_BANK7_ENABLE 0
330 * Memory bank enable bitmask, specifying which of the banks defined above
331 are actually present. MSB is for bank #7, LSB is for bank #0.
333 #define CFG_BANK_ENABLE 0x01
335 #define CFG_ODCR 0xff /* configures line driver impedances, */
336 /* see 8240 book for bit definitions */
337 #define CFG_PGMAX 0x32 /* how long the 8240 retains the */
338 /* currently accessed page in memory */
339 /* see 8240 book for details */
341 /* SDRAM 0 - 256MB */
342 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
343 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
345 /* stack in DCACHE @ 1GB (no backing mem) */
346 #if defined(USE_DINK32)
347 #define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
348 #define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
350 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
351 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
355 #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
356 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
358 /* Flash, config addrs, etc */
359 #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
360 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
362 #define CFG_DBAT0L CFG_IBAT0L
363 #define CFG_DBAT0U CFG_IBAT0U
364 #define CFG_DBAT1L CFG_IBAT1L
365 #define CFG_DBAT1U CFG_IBAT1U
366 #define CFG_DBAT2L CFG_IBAT2L
367 #define CFG_DBAT2U CFG_IBAT2U
368 #define CFG_DBAT3L CFG_IBAT3L
369 #define CFG_DBAT3U CFG_IBAT3U
372 * For booting Linux, the board info and command line data
373 * have to be in the first 8 MB of memory, since this is
374 * the maximum mapped by the Linux kernel during initialization.
376 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
377 /*-----------------------------------------------------------------------
380 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
381 #define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
383 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
384 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
386 /*-----------------------------------------------------------------------
387 * Cache Configuration
389 #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
390 #if defined(CONFIG_CMD_KGDB)
391 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
396 * Internal Definitions
400 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
401 #define BOOTFLAG_WARM 0x02 /* Software reboot */
404 /* values according to the manual */
406 #define CONFIG_DRAM_50MHZ 1
407 #define CONFIG_SDRAM_50MHZ
410 #define NR_8259_INTS 1
413 #define CONFIG_DISK_SPINUP_TIME 1000000
416 #endif /* __CONFIG_H */