2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T1024/T1023 RDB board configuration file
14 /* High Level Configuration Options */
15 #define CONFIG_DISPLAY_BOARDINFO
17 #define CONFIG_E500 /* BOOKE e500 family */
18 #define CONFIG_E500MC /* BOOKE e500mc family */
19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
20 #define CONFIG_MP /* support multiple processors */
21 #define CONFIG_ENABLE_36BIT_PHYS
23 #ifdef CONFIG_PHYS_64BIT
24 #define CONFIG_ADDR_MAP 1
25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
29 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
30 #define CONFIG_FSL_IFC /* Enable IFC Support */
32 #define CONFIG_FSL_LAW /* Use common FSL init code */
33 #define CONFIG_ENV_OVERWRITE
35 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
37 /* support deep sleep */
38 #ifdef CONFIG_PPC_T1024
39 #define CONFIG_DEEP_SLEEP
41 #if defined(CONFIG_DEEP_SLEEP)
42 #define CONFIG_SILENT_CONSOLE
43 #define CONFIG_BOARD_EARLY_INIT_F
46 #ifdef CONFIG_RAMBOOT_PBL
47 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
48 #if defined(CONFIG_T1024RDB)
49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
50 #elif defined(CONFIG_T1023RDB)
51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
53 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
54 #define CONFIG_SPL_SERIAL_SUPPORT
55 #define CONFIG_SPL_FLUSH_IMAGE
56 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
57 #define CONFIG_FSL_LAW /* Use common FSL init code */
58 #define CONFIG_SYS_TEXT_BASE 0x30001000
59 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
60 #define CONFIG_SPL_PAD_TO 0x40000
61 #define CONFIG_SPL_MAX_SIZE 0x28000
62 #define RESET_VECTOR_OFFSET 0x27FFC
63 #define BOOT_PAGE_OFFSET 0x27000
64 #ifdef CONFIG_SPL_BUILD
65 #define CONFIG_SPL_SKIP_RELOCATE
66 #define CONFIG_SPL_COMMON_INIT_DDR
67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
68 #define CONFIG_SYS_NO_FLASH
72 #define CONFIG_SPL_NAND_SUPPORT
73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
74 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
75 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
76 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
78 #define CONFIG_SPL_NAND_BOOT
81 #ifdef CONFIG_SPIFLASH
82 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
83 #define CONFIG_SPL_SPI_SUPPORT
84 #define CONFIG_SPL_SPI_FLASH_SUPPORT
85 #define CONFIG_SPL_SPI_FLASH_MINIMAL
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
91 #ifndef CONFIG_SPL_BUILD
92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
94 #define CONFIG_SPL_SPI_BOOT
98 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
99 #define CONFIG_SPL_MMC_SUPPORT
100 #define CONFIG_SPL_MMC_MINIMAL
101 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
102 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
103 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
104 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
105 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
106 #ifndef CONFIG_SPL_BUILD
107 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
109 #define CONFIG_SPL_MMC_BOOT
112 #endif /* CONFIG_RAMBOOT_PBL */
114 #ifndef CONFIG_SYS_TEXT_BASE
115 #define CONFIG_SYS_TEXT_BASE 0xeff40000
118 #ifndef CONFIG_RESET_VECTOR_ADDRESS
119 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
122 #ifndef CONFIG_SYS_NO_FLASH
123 #define CONFIG_FLASH_CFI_DRIVER
124 #define CONFIG_SYS_FLASH_CFI
125 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
128 /* PCIe Boot - Master */
129 #define CONFIG_SRIO_PCIE_BOOT_MASTER
131 * for slave u-boot IMAGE instored in master memory space,
132 * PHYS must be aligned based on the SIZE
134 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
135 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
136 #ifdef CONFIG_PHYS_64BIT
137 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
138 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
140 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
141 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
144 * for slave UCODE and ENV instored in master memory space,
145 * PHYS must be aligned based on the SIZE
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
149 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
151 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
152 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
154 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
155 /* slave core release by master*/
156 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
157 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
159 /* PCIe Boot - Slave */
160 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
161 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
162 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
163 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
164 /* Set 1M boot space for PCIe boot */
165 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
166 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
167 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
168 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
169 #define CONFIG_SYS_NO_FLASH
172 #if defined(CONFIG_SPIFLASH)
173 #define CONFIG_SYS_EXTRA_ENV_RELOC
174 #define CONFIG_ENV_IS_IN_SPI_FLASH
175 #define CONFIG_ENV_SPI_BUS 0
176 #define CONFIG_ENV_SPI_CS 0
177 #define CONFIG_ENV_SPI_MAX_HZ 10000000
178 #define CONFIG_ENV_SPI_MODE 0
179 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
180 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
181 #if defined(CONFIG_T1024RDB)
182 #define CONFIG_ENV_SECT_SIZE 0x10000
183 #elif defined(CONFIG_T1023RDB)
184 #define CONFIG_ENV_SECT_SIZE 0x40000
186 #elif defined(CONFIG_SDCARD)
187 #define CONFIG_SYS_EXTRA_ENV_RELOC
188 #define CONFIG_ENV_IS_IN_MMC
189 #define CONFIG_SYS_MMC_ENV_DEV 0
190 #define CONFIG_ENV_SIZE 0x2000
191 #define CONFIG_ENV_OFFSET (512 * 0x800)
192 #elif defined(CONFIG_NAND)
193 #define CONFIG_SYS_EXTRA_ENV_RELOC
194 #define CONFIG_ENV_IS_IN_NAND
195 #define CONFIG_ENV_SIZE 0x2000
196 #if defined(CONFIG_T1024RDB)
197 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
198 #elif defined(CONFIG_T1023RDB)
199 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
201 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
202 #define CONFIG_ENV_IS_IN_REMOTE
203 #define CONFIG_ENV_ADDR 0xffe20000
204 #define CONFIG_ENV_SIZE 0x2000
205 #elif defined(CONFIG_ENV_IS_NOWHERE)
206 #define CONFIG_ENV_SIZE 0x2000
208 #define CONFIG_ENV_IS_IN_FLASH
209 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
210 #define CONFIG_ENV_SIZE 0x2000
211 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
215 unsigned long get_board_sys_clk(void);
216 unsigned long get_board_ddr_clk(void);
219 #define CONFIG_SYS_CLK_FREQ 100000000
220 #define CONFIG_DDR_CLK_FREQ 100000000
223 * These can be toggled for performance analysis, otherwise use default.
225 #define CONFIG_SYS_CACHE_STASHING
226 #define CONFIG_BACKSIDE_L2_CACHE
227 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
228 #define CONFIG_BTB /* toggle branch predition */
229 #define CONFIG_DDR_ECC
230 #ifdef CONFIG_DDR_ECC
231 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
232 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
235 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
236 #define CONFIG_SYS_MEMTEST_END 0x00400000
237 #define CONFIG_SYS_ALT_MEMTEST
238 #define CONFIG_PANIC_HANG /* do not reset board on panic */
241 * Config the L3 Cache as L3 SRAM
243 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
244 #define CONFIG_SYS_L3_SIZE (256 << 10)
245 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
246 #ifdef CONFIG_RAMBOOT_PBL
247 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
249 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
250 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
251 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
252 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
254 #ifdef CONFIG_PHYS_64BIT
255 #define CONFIG_SYS_DCSRBAR 0xf0000000
256 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
260 #define CONFIG_ID_EEPROM
261 #define CONFIG_SYS_I2C_EEPROM_NXID
262 #define CONFIG_SYS_EEPROM_BUS_NUM 0
263 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
264 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
265 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
271 #define CONFIG_VERY_BIG_RAM
272 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
273 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
274 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
275 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
276 #define CONFIG_FSL_DDR_INTERACTIVE
277 #if defined(CONFIG_T1024RDB)
278 #define CONFIG_DDR_SPD
279 #define CONFIG_SYS_FSL_DDR3
280 #define CONFIG_SYS_SPD_BUS_NUM 0
281 #define SPD_EEPROM_ADDRESS 0x51
282 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
283 #elif defined(CONFIG_T1023RDB)
284 #define CONFIG_SYS_FSL_DDR4
285 #define CONFIG_SYS_DDR_RAW_TIMING
286 #define CONFIG_SYS_SDRAM_SIZE 2048
292 #define CONFIG_SYS_FLASH_BASE 0xe8000000
293 #ifdef CONFIG_PHYS_64BIT
294 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
296 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
299 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
300 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
301 CSPR_PORT_SIZE_16 | \
304 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
306 /* NOR Flash Timing Params */
307 #if defined(CONFIG_T1024RDB)
308 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
309 #elif defined(CONFIG_T1023RDB)
310 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
311 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
313 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
314 FTIM0_NOR_TEADC(0x5) | \
315 FTIM0_NOR_TEAHC(0x5))
316 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
317 FTIM1_NOR_TRAD_NOR(0x1A) |\
318 FTIM1_NOR_TSEQRAD_NOR(0x13))
319 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
320 FTIM2_NOR_TCH(0x4) | \
321 FTIM2_NOR_TWPH(0x0E) | \
323 #define CONFIG_SYS_NOR_FTIM3 0x0
325 #define CONFIG_SYS_FLASH_QUIET_TEST
326 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
328 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
329 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
330 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
331 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
333 #define CONFIG_SYS_FLASH_EMPTY_INFO
334 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
336 #ifdef CONFIG_T1024RDB
338 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
339 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
340 #define CONFIG_SYS_CSPR2_EXT (0xf)
341 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
345 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
346 #define CONFIG_SYS_CSOR2 0x0
348 /* CPLD Timing parameters for IFC CS2 */
349 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
350 FTIM0_GPCM_TEADC(0x0e) | \
351 FTIM0_GPCM_TEAHC(0x0e))
352 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
353 FTIM1_GPCM_TRAD(0x1f))
354 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
355 FTIM2_GPCM_TCH(0x8) | \
356 FTIM2_GPCM_TWP(0x1f))
357 #define CONFIG_SYS_CS2_FTIM3 0x0
360 /* NAND Flash on IFC */
361 #define CONFIG_NAND_FSL_IFC
362 #define CONFIG_SYS_NAND_BASE 0xff800000
363 #ifdef CONFIG_PHYS_64BIT
364 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
366 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
368 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
369 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
370 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
371 | CSPR_MSEL_NAND /* MSEL = NAND */ \
373 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
375 #if defined(CONFIG_T1024RDB)
376 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
377 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
378 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
379 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
380 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
381 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
382 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
383 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
384 #elif defined(CONFIG_T1023RDB)
385 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
386 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
387 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
388 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
389 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
390 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
391 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
392 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
395 #define CONFIG_SYS_NAND_ONFI_DETECTION
396 /* ONFI NAND Flash mode0 Timing Params */
397 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
398 FTIM0_NAND_TWP(0x18) | \
399 FTIM0_NAND_TWCHT(0x07) | \
400 FTIM0_NAND_TWH(0x0a))
401 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
402 FTIM1_NAND_TWBE(0x39) | \
403 FTIM1_NAND_TRR(0x0e) | \
404 FTIM1_NAND_TRP(0x18))
405 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
406 FTIM2_NAND_TREH(0x0a) | \
407 FTIM2_NAND_TWHRE(0x1e))
408 #define CONFIG_SYS_NAND_FTIM3 0x0
410 #define CONFIG_SYS_NAND_DDR_LAW 11
411 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
412 #define CONFIG_SYS_MAX_NAND_DEVICE 1
413 #define CONFIG_CMD_NAND
415 #if defined(CONFIG_NAND)
416 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
417 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
418 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
419 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
420 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
421 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
422 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
423 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
424 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
425 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
426 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
427 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
428 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
429 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
430 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
431 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
433 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
434 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
435 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
436 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
437 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
438 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
439 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
440 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
441 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
442 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
443 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
444 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
445 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
446 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
447 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
448 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
451 #ifdef CONFIG_SPL_BUILD
452 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
454 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
457 #if defined(CONFIG_RAMBOOT_PBL)
458 #define CONFIG_SYS_RAMBOOT
461 #define CONFIG_BOARD_EARLY_INIT_R
462 #define CONFIG_MISC_INIT_R
464 #define CONFIG_HWCONFIG
466 /* define to use L1 as initial stack */
467 #define CONFIG_L1_INIT_RAM
468 #define CONFIG_SYS_INIT_RAM_LOCK
469 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
470 #ifdef CONFIG_PHYS_64BIT
471 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
473 /* The assembler doesn't like typecast */
474 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
475 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
476 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
478 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
482 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
484 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
485 GENERATED_GBL_DATA_SIZE)
486 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
488 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
489 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
492 #define CONFIG_CONS_INDEX 1
493 #define CONFIG_SYS_NS16550_SERIAL
494 #define CONFIG_SYS_NS16550_REG_SIZE 1
495 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
497 #define CONFIG_SYS_BAUDRATE_TABLE \
498 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
500 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
501 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
502 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
503 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
504 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
507 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
508 #ifdef CONFIG_FSL_DIU_FB
509 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
511 #define CONFIG_CMD_BMP
512 #define CONFIG_CFB_CONSOLE
513 #define CONFIG_VIDEO_SW_CURSOR
514 #define CONFIG_VGA_AS_SINGLE_DEVICE
515 #define CONFIG_VIDEO_LOGO
516 #define CONFIG_VIDEO_BMP_LOGO
517 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
519 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
520 * disable empty flash sector detection, which is I/O-intensive.
522 #undef CONFIG_SYS_FLASH_EMPTY_INFO
526 #define CONFIG_SYS_I2C
527 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
528 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
529 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
530 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
531 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
532 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
533 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
535 #define I2C_PCA6408_BUS_NUM 1
536 #define I2C_PCA6408_ADDR 0x20
538 /* I2C bus multiplexer */
539 #define I2C_MUX_CH_DEFAULT 0x8
545 #define CONFIG_RTC_DS1337 1
546 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
549 * eSPI - Enhanced SPI
551 #define CONFIG_SPI_FLASH_BAR
552 #define CONFIG_SF_DEFAULT_SPEED 10000000
553 #define CONFIG_SF_DEFAULT_MODE 0
557 * Memory space is mapped 1-1, but I/O space must start from 0.
559 #define CONFIG_PCI /* Enable PCI/PCIE */
560 #define CONFIG_PCIE1 /* PCIE controller 1 */
561 #define CONFIG_PCIE2 /* PCIE controller 2 */
562 #define CONFIG_PCIE3 /* PCIE controller 3 */
563 #ifdef CONFIG_PPC_T1040
564 #define CONFIG_PCIE4 /* PCIE controller 4 */
566 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
567 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
568 #define CONFIG_PCI_INDIRECT_BRIDGE
571 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
573 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
574 #ifdef CONFIG_PHYS_64BIT
575 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
576 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
578 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
579 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
581 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
582 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
583 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
584 #ifdef CONFIG_PHYS_64BIT
585 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
587 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
589 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
592 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
594 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
595 #ifdef CONFIG_PHYS_64BIT
596 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
597 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
599 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
600 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
602 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
603 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
604 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
605 #ifdef CONFIG_PHYS_64BIT
606 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
608 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
610 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
613 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
615 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
616 #ifdef CONFIG_PHYS_64BIT
617 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
618 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
620 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
621 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
623 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
624 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
625 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
626 #ifdef CONFIG_PHYS_64BIT
627 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
629 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
631 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
634 /* controller 4, Base address 203000, to be removed */
636 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
637 #ifdef CONFIG_PHYS_64BIT
638 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
639 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
641 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
642 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
644 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
645 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
646 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
647 #ifdef CONFIG_PHYS_64BIT
648 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
650 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
652 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
655 #define CONFIG_PCI_PNP /* do pci plug-and-play */
656 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
657 #define CONFIG_DOS_PARTITION
658 #endif /* CONFIG_PCI */
663 #define CONFIG_HAS_FSL_DR_USB
665 #ifdef CONFIG_HAS_FSL_DR_USB
666 #define CONFIG_USB_EHCI
667 #define CONFIG_USB_EHCI_FSL
668 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
676 #define CONFIG_FSL_ESDHC
677 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
678 #define CONFIG_GENERIC_MMC
679 #define CONFIG_DOS_PARTITION
683 #ifndef CONFIG_NOBQFMAN
684 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
685 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
686 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
687 #ifdef CONFIG_PHYS_64BIT
688 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
690 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
692 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
693 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
694 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
695 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
696 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
697 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
698 CONFIG_SYS_BMAN_CENA_SIZE)
699 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
700 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
701 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
702 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
703 #ifdef CONFIG_PHYS_64BIT
704 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
706 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
708 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
709 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
710 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
711 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
712 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
713 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
714 CONFIG_SYS_QMAN_CENA_SIZE)
715 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
716 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
718 #define CONFIG_SYS_DPAA_FMAN
720 #ifdef CONFIG_T1024RDB
724 /* Default address of microcode for the Linux FMan driver */
725 #if defined(CONFIG_SPIFLASH)
727 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
728 * env, so we got 0x110000.
730 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
731 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
732 #define CONFIG_SYS_QE_FW_ADDR 0x130000
733 #elif defined(CONFIG_SDCARD)
735 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
736 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
737 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
739 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
740 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
741 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
742 #elif defined(CONFIG_NAND)
743 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
744 #if defined(CONFIG_T1024RDB)
745 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
746 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
747 #elif defined(CONFIG_T1023RDB)
748 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
749 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
751 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
753 * Slave has no ucode locally, it can fetch this from remote. When implementing
754 * in two corenet boards, slave's ucode could be stored in master's memory
755 * space, the address can be mapped from slave TLB->slave LAW->
756 * slave SRIO or PCIE outbound window->master inbound window->
757 * master LAW->the ucode address in master's memory space.
759 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
760 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
762 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
763 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
764 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
766 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
767 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
768 #endif /* CONFIG_NOBQFMAN */
770 #ifdef CONFIG_SYS_DPAA_FMAN
771 #define CONFIG_FMAN_ENET
772 #define CONFIG_PHYLIB_10G
773 #define CONFIG_PHY_REALTEK
774 #define CONFIG_PHY_AQUANTIA
775 #if defined(CONFIG_T1024RDB)
776 #define RGMII_PHY1_ADDR 0x2
777 #define RGMII_PHY2_ADDR 0x6
778 #define SGMII_AQR_PHY_ADDR 0x2
779 #define FM1_10GEC1_PHY_ADDR 0x1
780 #elif defined(CONFIG_T1023RDB)
781 #define RGMII_PHY1_ADDR 0x1
782 #define SGMII_RTK_PHY_ADDR 0x3
783 #define SGMII_AQR_PHY_ADDR 0x2
787 #ifdef CONFIG_FMAN_ENET
788 #define CONFIG_MII /* MII PHY management */
789 #define CONFIG_ETHPRIME "FM1@DTSEC4"
790 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
794 * Dynamic MTD Partition support with mtdparts
796 #ifndef CONFIG_SYS_NO_FLASH
797 #define CONFIG_MTD_DEVICE
798 #define CONFIG_MTD_PARTITIONS
799 #define CONFIG_CMD_MTDPARTS
800 #define CONFIG_FLASH_CFI_MTD
801 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
803 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
804 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
805 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
806 "1m(uboot),5m(kernel),128k(dtb),-(user)"
812 #define CONFIG_LOADS_ECHO /* echo on for serial download */
813 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
816 * Command line configuration.
818 #define CONFIG_CMD_DATE
819 #define CONFIG_CMD_EEPROM
820 #define CONFIG_CMD_ERRATA
821 #define CONFIG_CMD_IRQ
822 #define CONFIG_CMD_REGINFO
825 #define CONFIG_CMD_PCI
829 * Miscellaneous configurable options
831 #define CONFIG_SYS_LONGHELP /* undef to save memory */
832 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
833 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
834 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
835 #ifdef CONFIG_CMD_KGDB
836 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
838 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
840 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
841 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
842 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
845 * For booting Linux, the board info and command line data
846 * have to be in the first 64 MB of memory, since this is
847 * the maximum mapped by the Linux kernel during initialization.
849 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
850 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
852 #ifdef CONFIG_CMD_KGDB
853 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
857 * Environment Configuration
859 #define CONFIG_ROOTPATH "/opt/nfsroot"
860 #define CONFIG_BOOTFILE "uImage"
861 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
862 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
863 #define CONFIG_BAUDRATE 115200
864 #define __USB_PHY_TYPE utmi
866 #ifdef CONFIG_PPC_T1024
867 #define CONFIG_BOARDNAME t1024rdb
868 #define BANK_INTLV cs0_cs1
870 #define CONFIG_BOARDNAME t1023rdb
871 #define BANK_INTLV null
874 #define CONFIG_EXTRA_ENV_SETTINGS \
875 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
876 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
877 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
878 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
879 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
880 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
881 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
882 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
883 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
885 "tftpflash=tftpboot $loadaddr $uboot && " \
886 "protect off $ubootaddr +$filesize && " \
887 "erase $ubootaddr +$filesize && " \
888 "cp.b $loadaddr $ubootaddr $filesize && " \
889 "protect on $ubootaddr +$filesize && " \
890 "cmp.b $loadaddr $ubootaddr $filesize\0" \
891 "consoledev=ttyS0\0" \
892 "ramdiskaddr=2000000\0" \
893 "fdtaddr=1e00000\0" \
896 #define CONFIG_LINUX \
897 "setenv bootargs root=/dev/ram rw " \
898 "console=$consoledev,$baudrate $othbootargs;" \
899 "setenv ramdiskaddr 0x02000000;" \
900 "setenv fdtaddr 0x00c00000;" \
901 "setenv loadaddr 0x1000000;" \
902 "bootm $loadaddr $ramdiskaddr $fdtaddr"
904 #define CONFIG_NFSBOOTCOMMAND \
905 "setenv bootargs root=/dev/nfs rw " \
906 "nfsroot=$serverip:$rootpath " \
907 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
908 "console=$consoledev,$baudrate $othbootargs;" \
909 "tftp $loadaddr $bootfile;" \
910 "tftp $fdtaddr $fdtfile;" \
911 "bootm $loadaddr - $fdtaddr"
913 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
915 /* Hash command with SHA acceleration supported in hardware */
916 #ifdef CONFIG_FSL_CAAM
917 #define CONFIG_CMD_HASH
918 #define CONFIG_SHA_HW_ACCEL
921 #include <asm/fsl_secure_boot.h>
923 #endif /* __T1024RDB_H */