2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * T1040 QDS board configuration file
30 #ifdef CONFIG_RAMBOOT_PBL
31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
37 /* High Level Configuration Options */
38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
39 #define CONFIG_MP /* support multiple processors */
41 /* support deep sleep */
42 #define CONFIG_DEEP_SLEEP
44 #ifndef CONFIG_RESET_VECTOR_ADDRESS
45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
49 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
50 #define CONFIG_PCI_INDIRECT_BRIDGE
51 #define CONFIG_PCIE1 /* PCIE controller 1 */
52 #define CONFIG_PCIE2 /* PCIE controller 2 */
53 #define CONFIG_PCIE3 /* PCIE controller 3 */
54 #define CONFIG_PCIE4 /* PCIE controller 4 */
56 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
57 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
59 #define CONFIG_ENV_OVERWRITE
61 #ifndef CONFIG_MTD_NOR_FLASH
63 #define CONFIG_FLASH_CFI_DRIVER
64 #define CONFIG_SYS_FLASH_CFI
65 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
68 #ifdef CONFIG_MTD_NOR_FLASH
69 #if defined(CONFIG_SPIFLASH)
70 #define CONFIG_SYS_EXTRA_ENV_RELOC
71 #define CONFIG_ENV_SPI_BUS 0
72 #define CONFIG_ENV_SPI_CS 0
73 #define CONFIG_ENV_SPI_MAX_HZ 10000000
74 #define CONFIG_ENV_SPI_MODE 0
75 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
76 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
77 #define CONFIG_ENV_SECT_SIZE 0x10000
78 #elif defined(CONFIG_SDCARD)
79 #define CONFIG_SYS_EXTRA_ENV_RELOC
80 #define CONFIG_SYS_MMC_ENV_DEV 0
81 #define CONFIG_ENV_SIZE 0x2000
82 #define CONFIG_ENV_OFFSET (512 * 1658)
83 #elif defined(CONFIG_NAND)
84 #define CONFIG_SYS_EXTRA_ENV_RELOC
85 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
86 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
88 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
89 #define CONFIG_ENV_SIZE 0x2000
90 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
92 #else /* CONFIG_MTD_NOR_FLASH */
93 #define CONFIG_ENV_SIZE 0x2000
94 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
98 unsigned long get_board_sys_clk(void);
99 unsigned long get_board_ddr_clk(void);
102 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
103 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
106 * These can be toggled for performance analysis, otherwise use default.
108 #define CONFIG_SYS_CACHE_STASHING
109 #define CONFIG_BACKSIDE_L2_CACHE
110 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
111 #define CONFIG_BTB /* toggle branch predition */
112 #define CONFIG_DDR_ECC
113 #ifdef CONFIG_DDR_ECC
114 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
115 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
118 #define CONFIG_ENABLE_36BIT_PHYS
120 #define CONFIG_ADDR_MAP
121 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
123 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
124 #define CONFIG_SYS_MEMTEST_END 0x00400000
125 #define CONFIG_SYS_ALT_MEMTEST
128 * Config the L3 Cache as L3 SRAM
130 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
132 #define CONFIG_SYS_DCSRBAR 0xf0000000
133 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
136 #define CONFIG_ID_EEPROM
137 #define CONFIG_SYS_I2C_EEPROM_NXID
138 #define CONFIG_SYS_EEPROM_BUS_NUM 0
139 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
140 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
141 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
142 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
147 #define CONFIG_VERY_BIG_RAM
148 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
149 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
151 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
152 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
154 #define CONFIG_DDR_SPD
155 #define CONFIG_FSL_DDR_INTERACTIVE
157 #define CONFIG_SYS_SPD_BUS_NUM 0
158 #define SPD_EEPROM_ADDRESS 0x51
160 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
165 #define CONFIG_SYS_FLASH_BASE 0xe0000000
166 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
168 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
169 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
171 CSPR_PORT_SIZE_16 | \
174 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
175 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
176 CSPR_PORT_SIZE_16 | \
179 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
184 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
186 /* NOR Flash Timing Params */
187 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
188 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
189 FTIM0_NOR_TEADC(0x5) | \
190 FTIM0_NOR_TEAHC(0x5))
191 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
192 FTIM1_NOR_TRAD_NOR(0x1A) |\
193 FTIM1_NOR_TSEQRAD_NOR(0x13))
194 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
195 FTIM2_NOR_TCH(0x4) | \
196 FTIM2_NOR_TWPH(0x0E) | \
198 #define CONFIG_SYS_NOR_FTIM3 0x0
200 #define CONFIG_SYS_FLASH_QUIET_TEST
201 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
203 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
204 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
205 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
206 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
208 #define CONFIG_SYS_FLASH_EMPTY_INFO
209 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
210 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
211 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
212 #define QIXIS_BASE 0xffdf0000
213 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
214 #define QIXIS_LBMAP_SWITCH 0x06
215 #define QIXIS_LBMAP_MASK 0x0f
216 #define QIXIS_LBMAP_SHIFT 0
217 #define QIXIS_LBMAP_DFLTBANK 0x00
218 #define QIXIS_LBMAP_ALTBANK 0x04
219 #define QIXIS_RST_CTL_RESET 0x31
220 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
221 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
222 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
223 #define QIXIS_RST_FORCE_MEM 0x01
225 #define CONFIG_SYS_CSPR3_EXT (0xf)
226 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
230 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
231 #define CONFIG_SYS_CSOR3 0x0
232 /* QIXIS Timing parameters for IFC CS3 */
233 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
234 FTIM0_GPCM_TEADC(0x0e) | \
235 FTIM0_GPCM_TEAHC(0x0e))
236 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
237 FTIM1_GPCM_TRAD(0x3f))
238 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
239 FTIM2_GPCM_TCH(0x8) | \
240 FTIM2_GPCM_TWP(0x1f))
241 #define CONFIG_SYS_CS3_FTIM3 0x0
243 #define CONFIG_NAND_FSL_IFC
244 #define CONFIG_SYS_NAND_BASE 0xff800000
245 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
247 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
248 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
249 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
250 | CSPR_MSEL_NAND /* MSEL = NAND */ \
252 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
254 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
255 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
256 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
257 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
258 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
259 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
260 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
262 #define CONFIG_SYS_NAND_ONFI_DETECTION
264 /* ONFI NAND Flash mode0 Timing Params */
265 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
266 FTIM0_NAND_TWP(0x18) | \
267 FTIM0_NAND_TWCHT(0x07) | \
268 FTIM0_NAND_TWH(0x0a))
269 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
270 FTIM1_NAND_TWBE(0x39) | \
271 FTIM1_NAND_TRR(0x0e) | \
272 FTIM1_NAND_TRP(0x18))
273 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
274 FTIM2_NAND_TREH(0x0a) | \
275 FTIM2_NAND_TWHRE(0x1e))
276 #define CONFIG_SYS_NAND_FTIM3 0x0
278 #define CONFIG_SYS_NAND_DDR_LAW 11
279 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
280 #define CONFIG_SYS_MAX_NAND_DEVICE 1
282 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
284 #if defined(CONFIG_NAND)
285 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
286 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
287 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
288 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
289 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
290 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
291 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
292 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
293 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
294 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
295 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
296 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
297 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
298 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
299 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
300 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
301 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
302 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
303 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
304 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
305 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
306 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
307 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
308 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
310 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
311 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
312 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
313 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
314 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
315 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
316 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
317 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
318 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
319 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
320 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
321 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
322 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
323 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
324 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
325 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
326 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
327 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
328 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
329 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
330 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
331 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
332 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
333 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
336 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
338 #if defined(CONFIG_RAMBOOT_PBL)
339 #define CONFIG_SYS_RAMBOOT
342 #define CONFIG_BOARD_EARLY_INIT_R
343 #define CONFIG_MISC_INIT_R
345 #define CONFIG_HWCONFIG
347 /* define to use L1 as initial stack */
348 #define CONFIG_L1_INIT_RAM
349 #define CONFIG_SYS_INIT_RAM_LOCK
350 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
351 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
353 /* The assembler doesn't like typecast */
354 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
355 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
356 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
357 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
359 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
360 GENERATED_GBL_DATA_SIZE)
361 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
363 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
364 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
366 /* Serial Port - controlled on board with jumper J8
370 #define CONFIG_CONS_INDEX 1
371 #define CONFIG_SYS_NS16550_SERIAL
372 #define CONFIG_SYS_NS16550_REG_SIZE 1
373 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
375 #define CONFIG_SYS_BAUDRATE_TABLE \
376 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
378 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
379 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
380 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
381 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
384 #define CONFIG_FSL_DIU_FB
385 #ifdef CONFIG_FSL_DIU_FB
386 #define CONFIG_FSL_DIU_CH7301
387 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
388 #define CONFIG_VIDEO_LOGO
389 #define CONFIG_VIDEO_BMP_LOGO
390 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
392 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
393 * disable empty flash sector detection, which is I/O-intensive.
395 #undef CONFIG_SYS_FLASH_EMPTY_INFO
399 #define CONFIG_SYS_I2C
400 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
401 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
402 #define CONFIG_SYS_FSL_I2C2_SPEED 50000
403 #define CONFIG_SYS_FSL_I2C3_SPEED 50000
404 #define CONFIG_SYS_FSL_I2C4_SPEED 50000
405 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
406 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
407 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
408 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
409 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
410 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
411 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
412 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
414 #define I2C_MUX_PCA_ADDR 0x77
415 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
417 /* I2C bus multiplexer */
418 #define I2C_MUX_CH_DEFAULT 0x8
419 #define I2C_MUX_CH_DIU 0xC
421 /* LDI/DVI Encoder for display */
422 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
423 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
429 #define CONFIG_RTC_DS3231 1
430 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
433 * eSPI - Enhanced SPI
435 #define CONFIG_SF_DEFAULT_SPEED 10000000
436 #define CONFIG_SF_DEFAULT_MODE 0
440 * Memory space is mapped 1-1, but I/O space must start from 0.
444 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
446 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
447 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
448 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
449 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
450 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
451 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
452 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
453 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
456 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
458 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
459 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
460 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
461 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
462 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
463 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
464 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
465 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
468 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
470 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
471 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
472 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
473 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
474 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
475 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
476 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
477 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
480 /* controller 4, Base address 203000 */
482 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
483 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
484 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
485 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
486 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
487 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
488 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
489 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
492 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
493 #endif /* CONFIG_PCI */
496 #define CONFIG_FSL_SATA_V2
497 #ifdef CONFIG_FSL_SATA_V2
498 #define CONFIG_SYS_SATA_MAX_DEVICE 2
500 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
501 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
503 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
504 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
512 #define CONFIG_HAS_FSL_DR_USB
514 #ifdef CONFIG_HAS_FSL_DR_USB
515 #ifdef CONFIG_USB_EHCI_HCD
516 #define CONFIG_USB_EHCI_FSL
517 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
522 #define CONFIG_FSL_ESDHC
523 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
524 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
525 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
529 #ifndef CONFIG_NOBQFMAN
530 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
531 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
532 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
533 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
534 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
535 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
536 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
537 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
538 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
539 CONFIG_SYS_BMAN_CENA_SIZE)
540 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
541 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
542 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
543 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
544 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
545 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
546 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
547 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
548 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
549 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
550 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
551 CONFIG_SYS_QMAN_CENA_SIZE)
552 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
553 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
555 #define CONFIG_SYS_DPAA_FMAN
556 #define CONFIG_SYS_DPAA_PME
560 /* Default address of microcode for the Linux Fman driver */
561 #if defined(CONFIG_SPIFLASH)
563 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
564 * env, so we got 0x110000.
566 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
567 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
568 #elif defined(CONFIG_SDCARD)
570 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
571 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
572 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
574 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
575 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
576 #elif defined(CONFIG_NAND)
577 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
578 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
580 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
581 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
582 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
584 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
585 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
586 #endif /* CONFIG_NOBQFMAN */
588 #ifdef CONFIG_SYS_DPAA_FMAN
589 #define CONFIG_FMAN_ENET
590 #define CONFIG_PHYLIB_10G
591 #define CONFIG_PHY_VITESSE
592 #define CONFIG_PHY_REALTEK
593 #define CONFIG_PHY_TERANETICS
594 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
595 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
596 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
597 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
600 #ifdef CONFIG_FMAN_ENET
601 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
602 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
604 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
605 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
606 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
607 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
609 #define CONFIG_MII /* MII PHY management */
610 #define CONFIG_ETHPRIME "FM1@DTSEC1"
613 /* Enable VSC9953 L2 Switch driver */
614 #define CONFIG_VSC9953
615 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
616 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
619 * Dynamic MTD Partition support with mtdparts
621 #ifdef CONFIG_MTD_NOR_FLASH
622 #define CONFIG_MTD_DEVICE
623 #define CONFIG_MTD_PARTITIONS
624 #define CONFIG_FLASH_CFI_MTD
630 #define CONFIG_LOADS_ECHO /* echo on for serial download */
631 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
634 * Miscellaneous configurable options
636 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
639 * For booting Linux, the board info and command line data
640 * have to be in the first 64 MB of memory, since this is
641 * the maximum mapped by the Linux kernel during initialization.
643 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
644 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
646 #ifdef CONFIG_CMD_KGDB
647 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
651 * Environment Configuration
653 #define CONFIG_ROOTPATH "/opt/nfsroot"
654 #define CONFIG_BOOTFILE "uImage"
655 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
657 /* default location for tftp and bootm */
658 #define CONFIG_LOADADDR 1000000
660 #define __USB_PHY_TYPE utmi
662 #define CONFIG_EXTRA_ENV_SETTINGS \
663 "hwconfig=fsl_ddr:bank_intlv=auto;" \
664 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
666 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
667 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
668 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
669 "tftpflash=tftpboot $loadaddr $uboot && " \
670 "protect off $ubootaddr +$filesize && " \
671 "erase $ubootaddr +$filesize && " \
672 "cp.b $loadaddr $ubootaddr $filesize && " \
673 "protect on $ubootaddr +$filesize && " \
674 "cmp.b $loadaddr $ubootaddr $filesize\0" \
675 "consoledev=ttyS0\0" \
676 "ramdiskaddr=2000000\0" \
677 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
678 "fdtaddr=1e00000\0" \
679 "fdtfile=t1040qds/t1040qds.dtb\0" \
682 #define CONFIG_LINUX \
683 "setenv bootargs root=/dev/ram rw " \
684 "console=$consoledev,$baudrate $othbootargs;" \
685 "setenv ramdiskaddr 0x02000000;" \
686 "setenv fdtaddr 0x00c00000;" \
687 "setenv loadaddr 0x1000000;" \
688 "bootm $loadaddr $ramdiskaddr $fdtaddr"
690 #define CONFIG_HDBOOT \
691 "setenv bootargs root=/dev/$bdev rw " \
692 "console=$consoledev,$baudrate $othbootargs;" \
693 "tftp $loadaddr $bootfile;" \
694 "tftp $fdtaddr $fdtfile;" \
695 "bootm $loadaddr - $fdtaddr"
697 #define CONFIG_NFSBOOTCOMMAND \
698 "setenv bootargs root=/dev/nfs rw " \
699 "nfsroot=$serverip:$rootpath " \
700 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "tftp $loadaddr $bootfile;" \
703 "tftp $fdtaddr $fdtfile;" \
704 "bootm $loadaddr - $fdtaddr"
706 #define CONFIG_RAMBOOTCOMMAND \
707 "setenv bootargs root=/dev/ram rw " \
708 "console=$consoledev,$baudrate $othbootargs;" \
709 "tftp $ramdiskaddr $ramdiskfile;" \
710 "tftp $loadaddr $bootfile;" \
711 "tftp $fdtaddr $fdtfile;" \
712 "bootm $loadaddr $ramdiskaddr $fdtaddr"
714 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
716 #include <asm/fsl_secure_boot.h>
718 #endif /* __CONFIG_H */