2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * T2080/T2081 QDS board configuration file
14 #define CONFIG_DISPLAY_BOARDINFO
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17 #define CONFIG_USB_EHCI
18 #if defined(CONFIG_PPC_T2080)
19 #define CONFIG_T2080QDS
20 #define CONFIG_FSL_SATA_V2
21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
22 #define CONFIG_SRIO1 /* SRIO port 1 */
23 #define CONFIG_SRIO2 /* SRIO port 2 */
24 #elif defined(CONFIG_PPC_T2081)
25 #define CONFIG_T2081QDS
28 /* High Level Configuration Options */
30 #define CONFIG_E500 /* BOOKE e500 family */
31 #define CONFIG_E500MC /* BOOKE e500mc family */
32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
33 #define CONFIG_MP /* support multiple processors */
34 #define CONFIG_ENABLE_36BIT_PHYS
36 #ifdef CONFIG_PHYS_64BIT
37 #define CONFIG_ADDR_MAP 1
38 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
43 #define CONFIG_FSL_IFC /* Enable IFC Support */
44 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
45 #define CONFIG_FSL_LAW /* Use common FSL init code */
46 #define CONFIG_ENV_OVERWRITE
48 #ifdef CONFIG_RAMBOOT_PBL
49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
50 #if defined(CONFIG_PPC_T2080)
51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
52 #elif defined(CONFIG_PPC_T2081)
53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
56 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
57 #define CONFIG_SPL_SERIAL_SUPPORT
58 #define CONFIG_SPL_FLUSH_IMAGE
59 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
60 #define CONFIG_SPL_LIBGENERIC_SUPPORT
61 #define CONFIG_FSL_LAW /* Use common FSL init code */
62 #define CONFIG_SYS_TEXT_BASE 0x00201000
63 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
64 #define CONFIG_SPL_PAD_TO 0x40000
65 #define CONFIG_SPL_MAX_SIZE 0x28000
66 #define RESET_VECTOR_OFFSET 0x27FFC
67 #define BOOT_PAGE_OFFSET 0x27000
68 #ifdef CONFIG_SPL_BUILD
69 #define CONFIG_SPL_SKIP_RELOCATE
70 #define CONFIG_SPL_COMMON_INIT_DDR
71 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
72 #define CONFIG_SYS_NO_FLASH
76 #define CONFIG_SPL_NAND_SUPPORT
77 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
78 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
79 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
80 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
82 #define CONFIG_SPL_NAND_BOOT
85 #ifdef CONFIG_SPIFLASH
86 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
87 #define CONFIG_SPL_SPI_SUPPORT
88 #define CONFIG_SPL_SPI_FLASH_SUPPORT
89 #define CONFIG_SPL_SPI_FLASH_MINIMAL
90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
93 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
94 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
95 #ifndef CONFIG_SPL_BUILD
96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
98 #define CONFIG_SPL_SPI_BOOT
102 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
103 #define CONFIG_SPL_MMC_SUPPORT
104 #define CONFIG_SPL_MMC_MINIMAL
105 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
106 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
107 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
108 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
109 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
110 #ifndef CONFIG_SPL_BUILD
111 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
113 #define CONFIG_SPL_MMC_BOOT
116 #endif /* CONFIG_RAMBOOT_PBL */
118 #define CONFIG_SRIO_PCIE_BOOT_MASTER
119 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
120 /* Set 1M boot space */
121 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
122 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
123 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
124 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
125 #define CONFIG_SYS_NO_FLASH
128 #ifndef CONFIG_SYS_TEXT_BASE
129 #define CONFIG_SYS_TEXT_BASE 0xeff40000
132 #ifndef CONFIG_RESET_VECTOR_ADDRESS
133 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
137 * These can be toggled for performance analysis, otherwise use default.
139 #define CONFIG_SYS_CACHE_STASHING
140 #define CONFIG_BTB /* toggle branch predition */
141 #define CONFIG_DDR_ECC
142 #ifdef CONFIG_DDR_ECC
143 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
144 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
147 #ifndef CONFIG_SYS_NO_FLASH
148 #define CONFIG_FLASH_CFI_DRIVER
149 #define CONFIG_SYS_FLASH_CFI
150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
153 #if defined(CONFIG_SPIFLASH)
154 #define CONFIG_SYS_EXTRA_ENV_RELOC
155 #define CONFIG_ENV_IS_IN_SPI_FLASH
156 #define CONFIG_ENV_SPI_BUS 0
157 #define CONFIG_ENV_SPI_CS 0
158 #define CONFIG_ENV_SPI_MAX_HZ 10000000
159 #define CONFIG_ENV_SPI_MODE 0
160 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
161 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
162 #define CONFIG_ENV_SECT_SIZE 0x10000
163 #elif defined(CONFIG_SDCARD)
164 #define CONFIG_SYS_EXTRA_ENV_RELOC
165 #define CONFIG_ENV_IS_IN_MMC
166 #define CONFIG_SYS_MMC_ENV_DEV 0
167 #define CONFIG_ENV_SIZE 0x2000
168 #define CONFIG_ENV_OFFSET (512 * 0x800)
169 #elif defined(CONFIG_NAND)
170 #define CONFIG_SYS_EXTRA_ENV_RELOC
171 #define CONFIG_ENV_IS_IN_NAND
172 #define CONFIG_ENV_SIZE 0x2000
173 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
174 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
175 #define CONFIG_ENV_IS_IN_REMOTE
176 #define CONFIG_ENV_ADDR 0xffe20000
177 #define CONFIG_ENV_SIZE 0x2000
178 #elif defined(CONFIG_ENV_IS_NOWHERE)
179 #define CONFIG_ENV_SIZE 0x2000
181 #define CONFIG_ENV_IS_IN_FLASH
182 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
183 #define CONFIG_ENV_SIZE 0x2000
184 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
188 unsigned long get_board_sys_clk(void);
189 unsigned long get_board_ddr_clk(void);
192 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
193 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
196 * Config the L3 Cache as L3 SRAM
198 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
199 #define CONFIG_SYS_L3_SIZE (512 << 10)
200 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
201 #ifdef CONFIG_RAMBOOT_PBL
202 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
204 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
205 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
206 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
207 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
209 #define CONFIG_SYS_DCSRBAR 0xf0000000
210 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
213 #define CONFIG_ID_EEPROM
214 #define CONFIG_SYS_I2C_EEPROM_NXID
215 #define CONFIG_SYS_EEPROM_BUS_NUM 0
216 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
222 #define CONFIG_VERY_BIG_RAM
223 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
224 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
225 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
226 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
227 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
228 #define CONFIG_DDR_SPD
229 #define CONFIG_SYS_FSL_DDR3
230 #define CONFIG_FSL_DDR_INTERACTIVE
231 #define CONFIG_SYS_SPD_BUS_NUM 0
232 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
233 #define SPD_EEPROM_ADDRESS1 0x51
234 #define SPD_EEPROM_ADDRESS2 0x52
235 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
236 #define CTRL_INTLV_PREFERED cacheline
241 #define CONFIG_SYS_FLASH_BASE 0xe0000000
242 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
243 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
244 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
246 CSPR_PORT_SIZE_16 | \
249 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
250 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
251 CSPR_PORT_SIZE_16 | \
254 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
255 /* NOR Flash Timing Params */
256 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
258 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
259 FTIM0_NOR_TEADC(0x5) | \
260 FTIM0_NOR_TEAHC(0x5))
261 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
262 FTIM1_NOR_TRAD_NOR(0x1A) |\
263 FTIM1_NOR_TSEQRAD_NOR(0x13))
264 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
265 FTIM2_NOR_TCH(0x4) | \
266 FTIM2_NOR_TWPH(0x0E) | \
268 #define CONFIG_SYS_NOR_FTIM3 0x0
270 #define CONFIG_SYS_FLASH_QUIET_TEST
271 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
273 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
274 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
275 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
276 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
278 #define CONFIG_SYS_FLASH_EMPTY_INFO
279 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
280 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
282 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
283 #define QIXIS_BASE 0xffdf0000
284 #define QIXIS_LBMAP_SWITCH 6
285 #define QIXIS_LBMAP_MASK 0x0f
286 #define QIXIS_LBMAP_SHIFT 0
287 #define QIXIS_LBMAP_DFLTBANK 0x00
288 #define QIXIS_LBMAP_ALTBANK 0x04
289 #define QIXIS_LBMAP_NAND 0x09
290 #define QIXIS_LBMAP_SD 0x00
291 #define QIXIS_RCW_SRC_NAND 0x104
292 #define QIXIS_RCW_SRC_SD 0x040
293 #define QIXIS_RST_CTL_RESET 0x83
294 #define QIXIS_RST_FORCE_MEM 0x1
295 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
296 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
297 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
298 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
300 #define CONFIG_SYS_CSPR3_EXT (0xf)
301 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
305 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
306 #define CONFIG_SYS_CSOR3 0x0
307 /* QIXIS Timing parameters for IFC CS3 */
308 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
309 FTIM0_GPCM_TEADC(0x0e) | \
310 FTIM0_GPCM_TEAHC(0x0e))
311 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
312 FTIM1_GPCM_TRAD(0x3f))
313 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
314 FTIM2_GPCM_TCH(0x8) | \
315 FTIM2_GPCM_TWP(0x1f))
316 #define CONFIG_SYS_CS3_FTIM3 0x0
318 /* NAND Flash on IFC */
319 #define CONFIG_NAND_FSL_IFC
320 #define CONFIG_SYS_NAND_BASE 0xff800000
321 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
323 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
324 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
325 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
326 | CSPR_MSEL_NAND /* MSEL = NAND */ \
328 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
330 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
331 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
332 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
333 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
334 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
335 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
336 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
338 #define CONFIG_SYS_NAND_ONFI_DETECTION
340 /* ONFI NAND Flash mode0 Timing Params */
341 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
342 FTIM0_NAND_TWP(0x18) | \
343 FTIM0_NAND_TWCHT(0x07) | \
344 FTIM0_NAND_TWH(0x0a))
345 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
346 FTIM1_NAND_TWBE(0x39) | \
347 FTIM1_NAND_TRR(0x0e) | \
348 FTIM1_NAND_TRP(0x18))
349 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
350 FTIM2_NAND_TREH(0x0a) | \
351 FTIM2_NAND_TWHRE(0x1e))
352 #define CONFIG_SYS_NAND_FTIM3 0x0
354 #define CONFIG_SYS_NAND_DDR_LAW 11
355 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
356 #define CONFIG_SYS_MAX_NAND_DEVICE 1
357 #define CONFIG_CMD_NAND
358 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
360 #if defined(CONFIG_NAND)
361 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
362 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
363 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
364 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
365 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
366 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
367 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
368 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
369 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
370 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
371 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
372 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
373 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
374 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
375 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
376 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
377 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
378 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
379 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
380 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
381 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
382 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
383 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
384 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
386 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
387 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
388 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
389 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
390 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
391 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
392 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
393 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
394 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
395 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
396 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
397 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
398 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
399 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
400 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
401 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
402 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
403 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
404 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
405 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
406 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
407 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
408 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
409 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
412 #if defined(CONFIG_RAMBOOT_PBL)
413 #define CONFIG_SYS_RAMBOOT
416 #ifdef CONFIG_SPL_BUILD
417 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
419 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
422 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
423 #define CONFIG_MISC_INIT_R
424 #define CONFIG_HWCONFIG
426 /* define to use L1 as initial stack */
427 #define CONFIG_L1_INIT_RAM
428 #define CONFIG_SYS_INIT_RAM_LOCK
429 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
432 /* The assembler doesn't like typecast */
433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
434 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
435 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
436 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
437 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
438 GENERATED_GBL_DATA_SIZE)
439 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
440 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
441 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
446 #define CONFIG_CONS_INDEX 1
447 #define CONFIG_SYS_NS16550_SERIAL
448 #define CONFIG_SYS_NS16550_REG_SIZE 1
449 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
450 #define CONFIG_SYS_BAUDRATE_TABLE \
451 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
452 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
453 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
454 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
455 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
460 #define CONFIG_SYS_I2C
461 #define CONFIG_SYS_I2C_FSL
462 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
463 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
464 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
465 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
466 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
467 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
468 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
469 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
470 #define CONFIG_SYS_FSL_I2C_SPEED 100000
471 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
472 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
473 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
474 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
475 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
476 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
477 #define I2C_MUX_CH_DEFAULT 0x8
479 #define I2C_MUX_CH_VOL_MONITOR 0xa
481 /* Voltage monitor on channel 2*/
482 #define I2C_VOL_MONITOR_ADDR 0x40
483 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
484 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
485 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
487 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv"
488 #ifndef CONFIG_SPL_BUILD
491 #define CONFIG_VOL_MONITOR_IR36021_SET
492 #define CONFIG_VOL_MONITOR_IR36021_READ
493 /* The lowest and highest voltage allowed for T208xQDS */
494 #define VDD_MV_MIN 819
495 #define VDD_MV_MAX 1212
500 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
501 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
502 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
503 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
504 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
505 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
507 * for slave u-boot IMAGE instored in master memory space,
508 * PHYS must be aligned based on the SIZE
510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
512 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
513 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
515 * for slave UCODE and ENV instored in master memory space,
516 * PHYS must be aligned based on the SIZE
518 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
519 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
520 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
522 /* slave core release by master*/
523 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
524 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
527 * SRIO_PCIE_BOOT - SLAVE
529 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
530 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
531 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
532 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
536 * eSPI - Enhanced SPI
538 #ifdef CONFIG_SPI_FLASH
539 #ifndef CONFIG_SPL_BUILD
542 #define CONFIG_SPI_FLASH_BAR
543 #define CONFIG_SF_DEFAULT_SPEED 10000000
544 #define CONFIG_SF_DEFAULT_MODE 0
549 * Memory space is mapped 1-1, but I/O space must start from 0.
551 #define CONFIG_PCI /* Enable PCI/PCIE */
552 #define CONFIG_PCIE1 /* PCIE controller 1 */
553 #define CONFIG_PCIE2 /* PCIE controller 2 */
554 #define CONFIG_PCIE3 /* PCIE controller 3 */
555 #define CONFIG_PCIE4 /* PCIE controller 4 */
556 #define CONFIG_FSL_PCIE_RESET
557 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
558 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
559 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
560 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
561 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
562 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
563 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
564 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
565 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
566 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
567 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
569 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
570 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
571 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
572 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
573 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
574 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
575 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
576 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
577 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
579 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
580 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
581 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
582 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
583 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
584 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
585 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
586 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
587 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
589 /* controller 4, Base address 203000 */
590 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
591 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
592 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
593 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
594 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
595 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
596 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
599 #define CONFIG_PCI_INDIRECT_BRIDGE
600 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
601 #define CONFIG_PCI_PNP /* do pci plug-and-play */
602 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
603 #define CONFIG_DOS_PARTITION
607 #ifndef CONFIG_NOBQFMAN
608 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
609 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
610 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
611 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
612 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
613 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
614 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
615 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
616 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
617 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
618 CONFIG_SYS_BMAN_CENA_SIZE)
619 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
620 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
621 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
622 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
623 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
624 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
625 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
626 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
627 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
628 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
629 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
630 CONFIG_SYS_QMAN_CENA_SIZE)
631 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
632 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
634 #define CONFIG_SYS_DPAA_FMAN
635 #define CONFIG_SYS_DPAA_PME
636 #define CONFIG_SYS_PMAN
637 #define CONFIG_SYS_DPAA_DCE
638 #define CONFIG_SYS_DPAA_RMAN /* RMan */
639 #define CONFIG_SYS_INTERLAKEN
641 /* Default address of microcode for the Linux Fman driver */
642 #if defined(CONFIG_SPIFLASH)
644 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
645 * env, so we got 0x110000.
647 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
648 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
649 #elif defined(CONFIG_SDCARD)
651 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
652 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
653 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
655 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
656 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
657 #elif defined(CONFIG_NAND)
658 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
659 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
660 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
662 * Slave has no ucode locally, it can fetch this from remote. When implementing
663 * in two corenet boards, slave's ucode could be stored in master's memory
664 * space, the address can be mapped from slave TLB->slave LAW->
665 * slave SRIO or PCIE outbound window->master inbound window->
666 * master LAW->the ucode address in master's memory space.
668 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
669 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
671 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
672 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
674 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
675 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
676 #endif /* CONFIG_NOBQFMAN */
678 #ifdef CONFIG_SYS_DPAA_FMAN
679 #define CONFIG_FMAN_ENET
680 #define CONFIG_PHYLIB_10G
681 #define CONFIG_PHY_VITESSE
682 #define CONFIG_PHY_REALTEK
683 #define CONFIG_PHY_TERANETICS
684 #define RGMII_PHY1_ADDR 0x1
685 #define RGMII_PHY2_ADDR 0x2
686 #define FM1_10GEC1_PHY_ADDR 0x3
687 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
688 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
689 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
690 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
693 #ifdef CONFIG_FMAN_ENET
694 #define CONFIG_MII /* MII PHY management */
695 #define CONFIG_ETHPRIME "FM1@DTSEC3"
696 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
702 #ifdef CONFIG_FSL_SATA_V2
703 #define CONFIG_LIBATA
704 #define CONFIG_FSL_SATA
705 #define CONFIG_SYS_SATA_MAX_DEVICE 2
707 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
708 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
710 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
711 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
713 #define CONFIG_CMD_SATA
714 #define CONFIG_DOS_PARTITION
720 #ifdef CONFIG_USB_EHCI
721 #define CONFIG_USB_EHCI_FSL
722 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
723 #define CONFIG_HAS_FSL_DR_USB
730 #define CONFIG_FSL_ESDHC
731 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
732 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
733 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
734 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
735 #define CONFIG_GENERIC_MMC
736 #define CONFIG_DOS_PARTITION
737 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
741 * Dynamic MTD Partition support with mtdparts
743 #ifndef CONFIG_SYS_NO_FLASH
744 #define CONFIG_MTD_DEVICE
745 #define CONFIG_MTD_PARTITIONS
746 #define CONFIG_CMD_MTDPARTS
747 #define CONFIG_FLASH_CFI_MTD
748 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
750 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
751 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
752 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
753 "1m(uboot),5m(kernel),128k(dtb),-(user)"
759 #define CONFIG_LOADS_ECHO /* echo on for serial download */
760 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
763 * Command line configuration.
765 #define CONFIG_CMD_ERRATA
766 #define CONFIG_CMD_IRQ
767 #define CONFIG_CMD_REGINFO
770 #define CONFIG_CMD_PCI
773 /* Hash command with SHA acceleration supported in hardware */
774 #ifdef CONFIG_FSL_CAAM
775 #define CONFIG_CMD_HASH
776 #define CONFIG_SHA_HW_ACCEL
780 * Miscellaneous configurable options
782 #define CONFIG_SYS_LONGHELP /* undef to save memory */
783 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
784 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
785 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
786 #ifdef CONFIG_CMD_KGDB
787 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
789 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
791 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
792 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
793 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
796 * For booting Linux, the board info and command line data
797 * have to be in the first 64 MB of memory, since this is
798 * the maximum mapped by the Linux kernel during initialization.
800 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
801 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
803 #ifdef CONFIG_CMD_KGDB
804 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
805 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
809 * Environment Configuration
811 #define CONFIG_ROOTPATH "/opt/nfsroot"
812 #define CONFIG_BOOTFILE "uImage"
813 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
815 /* default location for tftp and bootm */
816 #define CONFIG_LOADADDR 1000000
817 #define CONFIG_BAUDRATE 115200
818 #define __USB_PHY_TYPE utmi
820 #define CONFIG_EXTRA_ENV_SETTINGS \
821 "hwconfig=fsl_ddr:" \
822 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
824 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
826 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
827 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
828 "tftpflash=tftpboot $loadaddr $uboot && " \
829 "protect off $ubootaddr +$filesize && " \
830 "erase $ubootaddr +$filesize && " \
831 "cp.b $loadaddr $ubootaddr $filesize && " \
832 "protect on $ubootaddr +$filesize && " \
833 "cmp.b $loadaddr $ubootaddr $filesize\0" \
834 "consoledev=ttyS0\0" \
835 "ramdiskaddr=2000000\0" \
836 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
837 "fdtaddr=1e00000\0" \
838 "fdtfile=t2080qds/t2080qds.dtb\0" \
842 * For emulation this causes u-boot to jump to the start of the
843 * proof point app code automatically
845 #define CONFIG_PROOF_POINTS \
846 "setenv bootargs root=/dev/$bdev rw " \
847 "console=$consoledev,$baudrate $othbootargs;" \
848 "cpu 1 release 0x29000000 - - -;" \
849 "cpu 2 release 0x29000000 - - -;" \
850 "cpu 3 release 0x29000000 - - -;" \
851 "cpu 4 release 0x29000000 - - -;" \
852 "cpu 5 release 0x29000000 - - -;" \
853 "cpu 6 release 0x29000000 - - -;" \
854 "cpu 7 release 0x29000000 - - -;" \
857 #define CONFIG_HVBOOT \
858 "setenv bootargs config-addr=0x60000000; " \
859 "bootm 0x01000000 - 0x00f00000"
862 "setenv bootargs root=/dev/$bdev rw " \
863 "console=$consoledev,$baudrate $othbootargs;" \
864 "cpu 1 release 0x01000000 - - -;" \
865 "cpu 2 release 0x01000000 - - -;" \
866 "cpu 3 release 0x01000000 - - -;" \
867 "cpu 4 release 0x01000000 - - -;" \
868 "cpu 5 release 0x01000000 - - -;" \
869 "cpu 6 release 0x01000000 - - -;" \
870 "cpu 7 release 0x01000000 - - -;" \
873 #define CONFIG_LINUX \
874 "setenv bootargs root=/dev/ram rw " \
875 "console=$consoledev,$baudrate $othbootargs;" \
876 "setenv ramdiskaddr 0x02000000;" \
877 "setenv fdtaddr 0x00c00000;" \
878 "setenv loadaddr 0x1000000;" \
879 "bootm $loadaddr $ramdiskaddr $fdtaddr"
881 #define CONFIG_HDBOOT \
882 "setenv bootargs root=/dev/$bdev rw " \
883 "console=$consoledev,$baudrate $othbootargs;" \
884 "tftp $loadaddr $bootfile;" \
885 "tftp $fdtaddr $fdtfile;" \
886 "bootm $loadaddr - $fdtaddr"
888 #define CONFIG_NFSBOOTCOMMAND \
889 "setenv bootargs root=/dev/nfs rw " \
890 "nfsroot=$serverip:$rootpath " \
891 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
892 "console=$consoledev,$baudrate $othbootargs;" \
893 "tftp $loadaddr $bootfile;" \
894 "tftp $fdtaddr $fdtfile;" \
895 "bootm $loadaddr - $fdtaddr"
897 #define CONFIG_RAMBOOTCOMMAND \
898 "setenv bootargs root=/dev/ram rw " \
899 "console=$consoledev,$baudrate $othbootargs;" \
900 "tftp $ramdiskaddr $ramdiskfile;" \
901 "tftp $loadaddr $bootfile;" \
902 "tftp $fdtaddr $fdtfile;" \
903 "bootm $loadaddr $ramdiskaddr $fdtaddr"
905 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
907 #include <asm/fsl_secure_boot.h>
909 #endif /* __T208xQDS_H */