2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * T4240 EMU board configuration file
29 #define CONFIG_T4240EMU
30 #define CONFIG_PHYS_64BIT
32 #define CONFIG_SYS_NO_FLASH 1
33 #define CONFIG_SYS_FSL_DDR_EMU 1
34 #define CONFIG_SYS_FSL_NO_QIXIS 1
35 #define CONFIG_SYS_FSL_NO_SERDES 1
39 #define CONFIG_CMD_CACHE
40 #define CONFIG_CMD_CACHE_FLUSH
42 #define CONFIG_ENV_IS_NOWHERE
43 #define CONFIG_ENV_SIZE 0x2000
45 #define CONFIG_SYS_CLK_FREQ 100000000
46 #define CONFIG_DDR_CLK_FREQ 133333333
47 #define CONFIG_FSL_TBCLK_EXTRA_DIV 100
53 #define CONFIG_SYS_SPD_BUS_NUM 1
54 #define SPD_EEPROM_ADDRESS1 0x51
55 #define SPD_EEPROM_ADDRESS2 0x52
56 #define SPD_EEPROM_ADDRESS3 0x53
57 #define SPD_EEPROM_ADDRESS4 0x54
58 #define SPD_EEPROM_ADDRESS5 0x55
59 #define SPD_EEPROM_ADDRESS6 0x56
60 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
61 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
66 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
67 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
68 /* NOR Flash Timing Params */
69 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
74 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0)
75 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
76 FTIM0_NOR_TEADC(0x1) | \
78 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
79 FTIM1_NOR_TRAD_NOR(0x1))
80 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
81 FTIM2_NOR_TCH(0x0) | \
83 #define CONFIG_SYS_NOR_FTIM3 0x04000000
84 #define CONFIG_SYS_IFC_CCR 0x01000000
86 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
87 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
88 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
89 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
90 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
91 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
92 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
93 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
97 #define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */
98 #define CONFIG_SYS_FSL_I2C2_SPEED 4000000
101 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
102 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
103 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
104 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
105 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
106 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
107 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
108 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
109 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
111 #define CONFIG_SYS_DPAA_FMAN
112 #define CONFIG_SYS_DPAA_PME
113 #define CONFIG_SYS_PMAN
114 #define CONFIG_SYS_DPAA_DCE
115 #define CONFIG_SYS_INTERLAKEN
117 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
118 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
119 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
120 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
124 #define CONFIG_BOOTDELAY 0
127 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
128 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
129 * interleaving. It can be cacheline, page, bank, superbank.
130 * See doc/README.fsl-ddr for details.
132 #ifdef CONFIG_PPC_T4240
133 #define CTRL_INTLV_PREFERED 3way_4KB
135 #define CTRL_INTLV_PREFERED cacheline
138 #define CONFIG_EXTRA_ENV_SETTINGS \
139 "hwconfig=fsl_ddr:" \
140 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
143 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
144 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
145 "consoledev=ttyS0\0" \
146 "ramdiskaddr=2000000\0" \
147 "ramdiskfile=t4240emu/ramdisk.uboot\0" \
149 "fdtfile=t4240emu/t4240emu.dtb\0" \
154 * For emulation this causes u-boot to jump to the start of the proof point
155 * app code automatically
157 #define CONFIG_PROOF_POINTS \
158 "setenv bootargs root=/dev/$bdev rw " \
159 "console=$consoledev,$baudrate $othbootargs;" \
160 "cpu 1 release 0x29000000 - - -;" \
161 "cpu 2 release 0x29000000 - - -;" \
162 "cpu 3 release 0x29000000 - - -;" \
163 "cpu 4 release 0x29000000 - - -;" \
164 "cpu 5 release 0x29000000 - - -;" \
165 "cpu 6 release 0x29000000 - - -;" \
166 "cpu 7 release 0x29000000 - - -;" \
169 #define CONFIG_HVBOOT \
170 "setenv bootargs config-addr=0x60000000; " \
171 "bootm 0x01000000 - 0x00f00000"
173 #define CONFIG_LINUX \
175 "setenv othbootargs ignore_loglevel;" \
176 "setenv bootargs root=/dev/ram rw " \
177 "console=$consoledev,$baudrate $othbootargs;" \
178 "setenv ramdiskaddr 0x02000000;" \
179 "setenv fdtaddr 0x00c00000;" \
180 "setenv loadaddr 0x1000000;" \
181 "bootm $loadaddr $ramdiskaddr $fdtaddr"
183 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
185 #endif /* __CONFIG_H */