2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37 #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
39 #ifdef CONFIG_LCD /* with LCD controller ? */
40 /* #define CONFIG_NEC_NL6648BC20 1 / * use NEC NL6648BC20 display */
43 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44 #undef CONFIG_8xx_CONS_SMC2
45 #undef CONFIG_8xx_CONS_NONE
46 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
48 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
50 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
53 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
55 #define CONFIG_BOARD_TYPES 1 /* support board types */
57 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
59 #undef CONFIG_BOOTARGS
60 #define CONFIG_BOOTCOMMAND \
62 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
63 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
66 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
67 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
69 #undef CONFIG_WATCHDOG /* watchdog disabled */
72 # undef CONFIG_STATUS_LED /* disturbs display */
74 # define CONFIG_STATUS_LED 1 /* Status LED enabled */
75 #endif /* CONFIG_LCD */
77 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
79 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
81 #define CONFIG_MAC_PARTITION
82 #define CONFIG_DOS_PARTITION
84 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
86 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
91 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
92 #include <cmd_confdefs.h>
95 * Miscellaneous configurable options
97 #define CFG_LONGHELP /* undef to save memory */
98 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
99 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
100 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
102 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
104 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
105 #define CFG_MAXARGS 16 /* max number of command args */
106 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
108 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
109 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
111 #define CFG_LOAD_ADDR 0x100000 /* default load address */
113 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
115 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
118 * Low Level Configuration Settings
119 * (address mappings, register initial values, etc.)
120 * You should know what you are doing if you make changes here.
122 /*-----------------------------------------------------------------------
123 * Internal Memory Mapped Register
125 #define CFG_IMMR 0xFFF00000
127 /*-----------------------------------------------------------------------
128 * Definitions for initial stack pointer and data area (in DPRAM)
130 #define CFG_INIT_RAM_ADDR CFG_IMMR
131 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
132 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
133 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
134 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
136 /*-----------------------------------------------------------------------
137 * Start addresses for the final memory configuration
138 * (Set up by the startup code)
139 * Please note that CFG_SDRAM_BASE _must_ start at 0
141 #define CFG_SDRAM_BASE 0x00000000
142 #define CFG_FLASH_BASE 0x40000000
143 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
144 #define CFG_MONITOR_BASE CFG_FLASH_BASE
145 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
148 * For booting Linux, the board info and command line data
149 * have to be in the first 8 MB of memory, since this is
150 * the maximum mapped by the Linux kernel during initialization.
152 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
154 /*-----------------------------------------------------------------------
157 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
158 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
160 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
161 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
163 #define CFG_ENV_IS_IN_FLASH 1
164 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
165 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
167 /* Address and size of Redundant Environment Sector */
168 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
169 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
171 /*-----------------------------------------------------------------------
172 * Hardware Information Block
174 #define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
175 #define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
176 #define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
178 /*-----------------------------------------------------------------------
179 * Cache Configuration
181 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
182 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
183 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
186 /*-----------------------------------------------------------------------
187 * SYPCR - System Protection Control 11-9
188 * SYPCR can only be written once after reset!
189 *-----------------------------------------------------------------------
190 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
192 #if defined(CONFIG_WATCHDOG)
193 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
194 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
196 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
199 /*-----------------------------------------------------------------------
200 * SIUMCR - SIU Module Configuration 11-6
201 *-----------------------------------------------------------------------
202 * PCMCIA config., multi-function pin tri-state
204 #ifndef CONFIG_CAN_DRIVER
205 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
206 #else /* we must activate GPL5 in the SIUMCR for CAN */
207 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
208 #endif /* CONFIG_CAN_DRIVER */
210 /*-----------------------------------------------------------------------
211 * TBSCR - Time Base Status and Control 11-26
212 *-----------------------------------------------------------------------
213 * Clear Reference Interrupt Status, Timebase freezing enabled
215 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
217 /*-----------------------------------------------------------------------
218 * RTCSC - Real-Time Clock Status and Control Register 11-27
219 *-----------------------------------------------------------------------
221 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
223 /*-----------------------------------------------------------------------
224 * PISCR - Periodic Interrupt Status and Control 11-31
225 *-----------------------------------------------------------------------
226 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
228 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
230 /*-----------------------------------------------------------------------
231 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
232 *-----------------------------------------------------------------------
233 * Reset PLL lock status sticky bit, timer expired status bit and timer
234 * interrupt status bit
236 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
238 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
240 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
241 #else /* up to 50 MHz we use a 1:1 clock */
242 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
243 #endif /* CONFIG_80MHz */
245 /*-----------------------------------------------------------------------
246 * SCCR - System Clock and reset Control Register 15-27
247 *-----------------------------------------------------------------------
248 * Set clock output, timebase and RTC source and divider,
249 * power management and some other internal clocks
251 #define SCCR_MASK SCCR_EBDF11
252 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
253 #define CFG_SCCR (/* SCCR_TBS | */ \
254 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
255 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
257 #else /* up to 50 MHz we use a 1:1 clock */
258 #define CFG_SCCR (SCCR_TBS | \
259 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
260 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
262 #endif /* CONFIG_80MHz */
264 /*-----------------------------------------------------------------------
266 *-----------------------------------------------------------------------
269 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
270 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
271 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
272 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
273 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
274 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
275 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
276 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
278 /*-----------------------------------------------------------------------
279 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
280 *-----------------------------------------------------------------------
283 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
285 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
286 #undef CONFIG_IDE_LED /* LED for ide not supported */
287 #undef CONFIG_IDE_RESET /* reset for ide not supported */
289 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
290 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
292 #define CFG_ATA_IDE0_OFFSET 0x0000
294 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
296 /* Offset for data I/O */
297 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
299 /* Offset for normal register accesses */
300 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
302 /* Offset for alternate registers */
303 #define CFG_ATA_ALT_OFFSET 0x0100
305 /*-----------------------------------------------------------------------
307 *-----------------------------------------------------------------------
310 /*#define CFG_DER 0x2002000F*/
314 * Init Memory Controller:
316 * BR0/1 and OR0/1 (FLASH)
319 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
320 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
322 /* used to re-map FLASH both when starting from SRAM or FLASH:
323 * restrict access enough to keep SRAM working (if any)
324 * but not too much to meddle with FLASH accesses
326 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
327 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
332 #if defined(CONFIG_80MHz)
333 /* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
334 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | 0 | OR_CSNT_SAM | \
335 OR_SCY_3_CLK | OR_EHTR | OR_BI)
336 #elif defined(CONFIG_66MHz)
337 /* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
338 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
339 OR_SCY_3_CLK | OR_EHTR | OR_BI)
341 /* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
342 #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
343 OR_SCY_2_CLK | OR_EHTR | OR_BI)
344 #endif /*CONFIG_??MHz */
346 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
347 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
348 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
350 #define CFG_OR1_REMAP CFG_OR0_REMAP
351 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
352 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
355 * BR2/3 and OR2/3 (SDRAM)
358 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
359 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
360 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
362 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
363 #define CFG_OR_TIMING_SDRAM 0x00000A00
365 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
366 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
368 #ifndef CONFIG_CAN_DRIVER
369 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
370 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
371 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
372 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
373 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
374 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
375 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
376 BR_PS_8 | BR_MS_UPMB | BR_V )
377 #endif /* CONFIG_CAN_DRIVER */
380 * Memory Periodic Timer Prescaler
382 * The Divider for PTA (refresh timer) configuration is based on an
383 * example SDRAM configuration (64 MBit, one bank). The adjustment to
384 * the number of chip selects (NCS) and the actually needed refresh
385 * rate is done by setting MPTPR.
387 * PTA is calculated from
388 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
390 * gclk CPU clock (not bus clock!)
391 * Trefresh Refresh cycle * 4 (four word bursts used)
393 * 4096 Rows from SDRAM example configuration
394 * 1000 factor s -> ms
395 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
396 * 4 Number of refresh cycles per period
397 * 64 Refresh cycle in ms per number of rows
398 * --------------------------------------------
399 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
401 * 50 MHz => 50.000.000 / Divider = 98
402 * 66 Mhz => 66.000.000 / Divider = 129
403 * 80 Mhz => 80.000.000 / Divider = 156
405 #if defined(CONFIG_80MHz)
406 #define CFG_MAMR_PTA 156
407 #elif defined(CONFIG_66MHz)
408 #define CFG_MAMR_PTA 129
410 #define CFG_MAMR_PTA 98
411 #endif /*CONFIG_??MHz */
414 * For 16 MBit, refresh rates could be 31.3 us
415 * (= 64 ms / 2K = 125 / quad bursts).
416 * For a simpler initialization, 15.6 us is used instead.
418 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
419 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
421 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
422 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
424 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
425 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
426 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
429 * MAMR settings for SDRAM
433 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
434 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
435 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
437 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
438 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
439 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
443 * Internal Definitions
447 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
448 #define BOOTFLAG_WARM 0x02 /* Software reboot */
450 #endif /* __CONFIG_H */