3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
31 #define CONFIG_MPC8220 1
32 #define CONFIG_YUKON8220 1 /* ... on Yukon board */
34 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
35 determine the CPU speed. */
36 #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
37 #define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
39 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
40 #define BOOTFLAG_WARM 0x02 /* Software reboot */
43 * Serial console configuration
46 /* Define this for PSC console
47 #define CONFIG_PSC_CONSOLE 1
50 #define CONFIG_EXTUART_CONSOLE 1
52 #ifdef CONFIG_EXTUART_CONSOLE
53 # define CONFIG_CONS_INDEX 1
54 # define CFG_NS16550_SERIAL
56 # define CFG_NS16550_REG_SIZE 1
57 # define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
58 # define CFG_NS16550_CLK 18432000
61 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
63 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
65 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
69 * Command line configuration.
71 #include <config_cmd_default.h>
73 #define CONFIG_CMD_BOOTD
74 #define CONFIG_CMD_CACHE
75 #define CONFIG_CMD_DHCP
76 #define CONFIG_CMD_DIAG
77 #define CONFIG_CMD_EEPROM
78 #define CONFIG_CMD_ELF
79 #define CONFIG_CMD_I2C
80 #define CONFIG_CMD_NET
81 #define CONFIG_CMD_NFS
82 #define CONFIG_CMD_PCI
83 #define CONFIG_CMD_PING
84 #define CONFIG_CMD_REGINFO
85 #define CONFIG_CMD_SDRAM
86 #define CONFIG_CMD_SNTP
89 #define CONFIG_NET_MULTI
95 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
96 #define CONFIG_BOOTARGS "root=/dev/ram rw"
97 #define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
98 #define CONFIG_HAS_ETH1
99 #define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
100 #define CONFIG_IPADDR 192.162.1.2
101 #define CONFIG_NETMASK 255.255.255.0
102 #define CONFIG_SERVERIP 192.162.1.1
103 #define CONFIG_GATEWAYIP 192.162.1.1
104 #define CONFIG_HOSTNAME yukon
105 #define CONFIG_OVERWRITE_ETHADDR_ONCE
111 #define CONFIG_HARD_I2C 1
112 #define CFG_I2C_MODULE 1
114 #define CFG_I2C_SPEED 100000 /* 100 kHz */
115 #define CFG_I2C_SLAVE 0x7F
118 * EEPROM configuration
120 #define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
121 #define CFG_I2C_EEPROM_ADDR_LEN 1
122 #define CFG_EEPROM_PAGE_WRITE_BITS 3
123 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
125 #define CFG_ENV_IS_IN_EEPROM 1
126 #define CFG_ENV_OFFSET 0
127 #define CFG_ENV_SIZE 256
130 /* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
131 else undefined it will boot from Intel Strata flash */
132 #define CFG_AMD_BOOT 1
135 * Flexbus Chipselect configuration
137 #if defined (CFG_AMD_BOOT)
138 #define CFG_CS0_BASE 0xfff0
139 #define CFG_CS0_MASK 0x00080000 /* 512 KB */
140 #define CFG_CS0_CTRL 0x003f0d40
142 #define CFG_CS1_BASE 0xfe00
143 #define CFG_CS1_MASK 0x01000000 /* 16 MB */
144 #define CFG_CS1_CTRL 0x003f1540
146 #define CFG_CS0_BASE 0xff00
147 #define CFG_CS0_MASK 0x01000000 /* 16 MB */
148 #define CFG_CS0_CTRL 0x003f1540
150 #define CFG_CS1_BASE 0xfe08
151 #define CFG_CS1_MASK 0x00080000 /* 512 KB */
152 #define CFG_CS1_CTRL 0x003f0d40
155 #define CFG_CS2_BASE 0xf100
156 #define CFG_CS2_MASK 0x00040000
157 #define CFG_CS2_CTRL 0x003f1140
159 #define CFG_CS3_BASE 0xf200
160 #define CFG_CS3_MASK 0x00040000
161 #define CFG_CS3_CTRL 0x003f1100
164 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
165 #define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
167 #if defined (CFG_AMD_BOOT)
168 #define CFG_AMD_BASE CFG_FLASH0_BASE
169 #define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
170 #define CFG_FLASH_BASE CFG_AMD_BASE
172 #define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
173 #define CFG_AMD_BASE CFG_FLASH1_BASE
174 #define CFG_FLASH_BASE CFG_INTEL_BASE
177 #define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
178 #define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
181 #define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
182 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
184 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
185 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
186 #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
187 #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
188 #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
190 #define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
191 #define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
193 #define CFG_FLASH_CHECKSUM
195 * Environment settings
197 #define CFG_ENV_IS_IN_FLASH 1
198 #if defined (CFG_AMD_BOOT)
199 #define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
200 #define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
201 #define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
202 #define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
203 #define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
204 #define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
206 #define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
207 #define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
208 #define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
209 #define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
210 #define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
211 #define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
214 #define CONFIG_ENV_OVERWRITE 1
216 #if defined CFG_ENV_IS_IN_FLASH
217 #undef CFG_ENV_IS_IN_NVRAM
218 #undef CFG_ENV_IS_IN_EEPROM
219 #elif defined CFG_ENV_IS_IN_NVRAM
220 #undef CFG_ENV_IS_IN_FLASH
221 #undef CFG_ENV_IS_IN_EEPROM
222 #elif defined CFG_ENV_IS_IN_EEPROM
223 #undef CFG_ENV_IS_IN_NVRAM
224 #undef CFG_ENV_IS_IN_FLASH
227 #ifndef CFG_JFFS2_FIRST_SECTOR
228 #define CFG_JFFS2_FIRST_SECTOR 0
230 #ifndef CFG_JFFS2_FIRST_BANK
231 #define CFG_JFFS2_FIRST_BANK 0
233 #ifndef CFG_JFFS2_NUM_BANKS
234 #define CFG_JFFS2_NUM_BANKS 1
236 #define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
241 #define CFG_MBAR 0xF0000000
242 #define CFG_SDRAM_BASE 0x00000000
243 #define CFG_DEFAULT_MBAR 0x80000000
244 #define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
245 #define CFG_SRAM_SIZE 0x8000
247 /* Use SRAM until RAM will be available */
248 #define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
249 #define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
251 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
252 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
253 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
255 #define CFG_MONITOR_BASE TEXT_BASE
256 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
257 # define CFG_RAMBOOT 1
260 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
261 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
262 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
264 /* SDRAM configuration */
265 #define CFG_SDRAM_TOTAL_BANKS 2
266 #define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
267 #define CFG_SDRAM_SPD_SIZE 0x40
268 #define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
270 /* SDRAM drive strength register */
271 #define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
272 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
273 (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
274 (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
275 (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
278 * Ethernet configuration
280 #define CONFIG_MPC8220_FEC 1
281 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
282 #define CONFIG_PHY_ADDR 0x18
286 * Miscellaneous configurable options
288 #define CFG_LONGHELP /* undef to save memory */
289 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
290 #if defined(CONFIG_CMD_KGDB)
291 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
293 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
295 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
296 #define CFG_MAXARGS 16 /* max number of command args */
297 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
299 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
300 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
302 #define CFG_LOAD_ADDR 0x100000 /* default load address */
304 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
306 #define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
307 #if defined(CONFIG_CMD_KGDB)
308 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
312 * Various low-level settings
314 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
315 #define CFG_HID0_FINAL HID0_ICE
317 #endif /* __CONFIG_H */