git.sur5r.net Git - u-boot/blob - include/configs/a320evb.h

   1 /*
   2  * (C) Copyright 2009 Faraday Technology
   3  * Po-Yu Chuang <ratbert@faraday-tech.com>
   4  *
   5  * Configuation settings for the Faraday A320 board.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 #include <asm/arch/a320.h>
  26
  27 /*
  28  * mach-type definition
  29  */
  30 #define MACH_TYPE_FARADAY       758
  31 #define CONFIG_MACH_TYPE        MACH_TYPE_FARADAY
  32
  33 /*
  34  * Linux kernel tagged list
  35  */
  36 #define CONFIG_CMDLINE_TAG
  37 #define CONFIG_SETUP_MEMORY_TAGS
  38
  39 /*
  40  * CPU and Board Configuration Options
  41  */
  42 #undef CONFIG_SKIP_LOWLEVEL_INIT
  43
  44 /*
  45  * Power Management Unit
  46  */
  47 #define CONFIG_FTPMU010_POWER
  48
  49 /*
  50  * Timer
  51  */
  52 #define CONFIG_SYS_HZ           1000    /* timer ticks per second */
  53
  54 /*
  55  * Real Time Clock
  56  */
  57 #define CONFIG_RTC_FTRTC010
  58
  59 /*
  60  * Serial console configuration
  61  */
  62
  63 /* FTUART is a high speed NS 16C550A compatible UART */
  64 #define CONFIG_BAUDRATE                 38400
  65 #define CONFIG_CONS_INDEX               1
  66 #define CONFIG_SYS_NS16550
  67 #define CONFIG_SYS_NS16550_SERIAL
  68 #define CONFIG_SYS_NS16550_COM1         0x98200000
  69 #define CONFIG_SYS_NS16550_REG_SIZE     -4
  70 #define CONFIG_SYS_NS16550_CLK          18432000
  71
  72 /*
  73  * Ethernet
  74  */
  75 #define CONFIG_FTMAC100
  76
  77 #define CONFIG_BOOTDELAY        3
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_CACHE
  85 #define CONFIG_CMD_DATE
  86 #define CONFIG_CMD_PING
  87
  88 /*
  89  * Miscellaneous configurable options
  90  */
  91 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
  92 #define CONFIG_SYS_PROMPT       "A320 # "       /* Monitor Command Prompt */
  93 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
  94
  95 /* Print Buffer Size */
  96 #define CONFIG_SYS_PBSIZE       \
  97         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  98
  99 /* max number of command args */
 100 #define CONFIG_SYS_MAXARGS      16
 101
 102 /* Boot Argument Buffer Size */
 103 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 104
 105 /*
 106  * Size of malloc() pool
 107  */
 108 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
 109
 110 /*
 111  * SDRAM controller configuration
 112  */
 113 #define CONFIG_SYS_FTSDMC020_TP0        (FTSDMC020_TP0_TRAS(2) |        \
 114                                          FTSDMC020_TP0_TRP(1)  |        \
 115                                          FTSDMC020_TP0_TRCD(1) |        \
 116                                          FTSDMC020_TP0_TRF(3)  |        \
 117                                          FTSDMC020_TP0_TWR(1)  |        \
 118                                          FTSDMC020_TP0_TCL(2))
 119
 120 #define CONFIG_SYS_FTSDMC020_TP1        (FTSDMC020_TP1_INI_PREC(4) |    \
 121                                          FTSDMC020_TP1_INI_REFT(8) |    \
 122                                          FTSDMC020_TP1_REF_INTV(0x180))
 123
 124 #define CONFIG_SYS_FTSDMC020_BANK0_BSR  (FTSDMC020_BANK_ENABLE   |      \
 125                                          FTSDMC020_BANK_DDW_X16  |      \
 126                                          FTSDMC020_BANK_DSZ_256M |      \
 127                                          FTSDMC020_BANK_MBW_32   |      \
 128                                          FTSDMC020_BANK_SIZE_64M)
 129
 130 /*
 131  * Physical Memory Map
 132  */
 133 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of DRAM */
 134 #define PHYS_SDRAM_1            0x10000000      /* SDRAM Bank #1 */
 135 #define PHYS_SDRAM_1_SIZE       0x04000000      /* 64 MB */
 136
 137 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 138 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 139                                         GENERATED_GBL_DATA_SIZE)
 140
 141 /*
 142  * Load address and memory test area should agree with
 143  * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
 144  */
 145 #define CONFIG_SYS_LOAD_ADDR            (PHYS_SDRAM_1 + 0x2000000)
 146
 147 /* memtest works on 63 MB in DRAM */
 148 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
 149 #define CONFIG_SYS_MEMTEST_END          (PHYS_SDRAM_1 + 0x3F00000)
 150
 151 #define CONFIG_SYS_TEXT_BASE            0
 152
 153 /*
 154  * Static memory controller configuration
 155  */
 156
 157 #define CONFIG_FTSMC020
 158 #include <faraday/ftsmc020.h>
 159
 160 #define FTSMC020_BANK0_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 161                                  FTSMC020_BANK_BASE(PHYS_FLASH_1) |     \
 162                                  FTSMC020_BANK_SIZE_1M            |     \
 163                                  FTSMC020_BANK_MBW_8)
 164
 165 #define FTSMC020_BANK0_TIMING   (FTSMC020_TPR_RBE      |        \
 166                                  FTSMC020_TPR_AST(3)   |        \
 167                                  FTSMC020_TPR_CTW(3)   |        \
 168                                  FTSMC020_TPR_ATI(0xf) |        \
 169                                  FTSMC020_TPR_AT2(3)   |        \
 170                                  FTSMC020_TPR_WTC(3)   |        \
 171                                  FTSMC020_TPR_AHT(3)   |        \
 172                                  FTSMC020_TPR_TRNA(0xf))
 173
 174 #define FTSMC020_BANK1_CONFIG   (FTSMC020_BANK_ENABLE             |     \
 175                                  FTSMC020_BANK_BASE(PHYS_FLASH_2) |     \
 176                                  FTSMC020_BANK_SIZE_32M           |     \
 177                                  FTSMC020_BANK_MBW_32)
 178
 179 #define FTSMC020_BANK1_TIMING   (FTSMC020_TPR_AST(3)   |        \
 180                                  FTSMC020_TPR_CTW(3)   |        \
 181                                  FTSMC020_TPR_ATI(0xf) |        \
 182                                  FTSMC020_TPR_AT2(3)   |        \
 183                                  FTSMC020_TPR_WTC(3)   |        \
 184                                  FTSMC020_TPR_AHT(3)   |        \
 185                                  FTSMC020_TPR_TRNA(0xf))
 186
 187 #define CONFIG_SYS_FTSMC020_CONFIGS     {                       \
 188         { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },      \
 189         { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },      \
 190 }
 191
 192 /*
 193  * FLASH and environment organization
 194  */
 195
 196 /* use CFI framework */
 197 #define CONFIG_SYS_FLASH_CFI
 198 #define CONFIG_FLASH_CFI_DRIVER
 199
 200 /* support JEDEC */
 201 #define CONFIG_FLASH_CFI_LEGACY
 202 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
 203
 204 #define PHYS_FLASH_1                    0x00000000
 205 #define PHYS_FLASH_2                    0x00400000
 206 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 207 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2, }
 208
 209 #define CONFIG_SYS_MONITOR_BASE         PHYS_FLASH_1
 210
 211 /* max number of memory banks */
 212 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 213
 214 /* max number of sectors on one chip */
 215 #define CONFIG_SYS_MAX_FLASH_SECT       512
 216
 217 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 218
 219 /* environments */
 220 #define CONFIG_ENV_IS_IN_FLASH
 221 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)
 222 #define CONFIG_ENV_SIZE                 0x20000
 223
 224 #endif  /* __CONFIG_H */