2 * Rick Bronson <rick@efn.org>
4 * Configuation settings for the AT91RM9200DK board.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * If we are developing, we might want to start armboot from ram
30 * so we MUST NOT initialize critical regs like mem-timing ...
32 #define CONFIG_INIT_CRITICAL
34 /* ARM asynchronous clock */
35 #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
36 #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
37 /* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
39 #define AT91_SLOW_CLOCK 32768 /* slow clock */
41 #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
42 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
43 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
44 #define CONFIG_SETUP_MEMORY_TAGS 1
45 #define CONFIG_INITRD_TAG 1
47 #ifdef CONFIG_INIT_CRITICAL
48 #define CFG_USE_MAIN_OSCILLATOR 1
50 #define MC_PUIA_VAL 0x00000000
51 #define MC_PUP_VAL 0x00000000
52 #define MC_PUER_VAL 0x00000000
53 #define MC_ASR_VAL 0x00000000
54 #define MC_AASR_VAL 0x00000000
55 #define EBI_CFGR_VAL 0x00000000
56 #define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
59 #define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
60 #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
61 #define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
64 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
65 #define PIOC_BSR_VAL 0x00000000
66 #define PIOC_PDR_VAL 0xFFFF0000
67 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
68 #define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
69 #define SDRAM 0x20000000 /* address of the SDRAM */
70 #define SDRAM1 0x20000080 /* address of the SDRAM */
71 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */
72 #define SDRC_MR_VAL 0x00000002 /* Precharge All */
73 #define SDRC_MR_VAL1 0x00000004 /* refresh */
74 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
75 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
76 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
77 #endif /* CONFIG_INIT_CRITICAL */
79 * Size of malloc() pool
81 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
82 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
84 #define CONFIG_BAUDRATE 115200
86 #define CFG_AT91C_BRGR_DIVISOR 33 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
92 /* define one of these to choose the DBGU, USART0 or USART1 as console */
97 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
99 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
101 #define CONFIG_BOOTDELAY 3
102 /* #define CONFIG_ENV_OVERWRITE 1 */
104 #define CONFIG_COMMANDS \
109 CFG_CMD_AUTOSCRIPT | \
114 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
115 #include <cmd_confdefs.h>
117 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
118 #define SECTORSIZE 512
120 #define ADDR_COLUMN 1
122 #define ADDR_COLUMN_PAGE 3
124 #define NAND_ChipID_UNKNOWN 0x00
125 #define NAND_MAX_FLOORS 1
126 #define NAND_MAX_CHIPS 1
128 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
129 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
131 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
132 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
134 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
136 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
137 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
138 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
139 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
140 /* the following are NOP's in our implementation */
141 #define NAND_CTL_CLRALE(nandptr)
142 #define NAND_CTL_SETALE(nandptr)
143 #define NAND_CTL_CLRCLE(nandptr)
144 #define NAND_CTL_SETCLE(nandptr)
146 #define CONFIG_NR_DRAM_BANKS 1
147 #define PHYS_SDRAM 0x20000000
148 #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
150 #define CFG_MEMTEST_START PHYS_SDRAM
151 #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
153 #define CONFIG_DRIVER_ETHER
154 #define CONFIG_NET_RETRY_COUNT 20
155 #define CONFIG_AT91C_USE_RMII
157 #define CONFIG_HAS_DATAFLASH 1
158 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
159 #define CFG_MAX_DATAFLASH_BANKS 2
160 #define CFG_MAX_DATAFLASH_PAGES 16384
161 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
162 #define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
164 #define PHYS_FLASH_1 0x10000000
165 #define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
166 #define CFG_FLASH_BASE PHYS_FLASH_1
167 #define CFG_MAX_FLASH_BANKS 1
168 #define CFG_MAX_FLASH_SECT 256
169 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
170 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
172 #undef CFG_ENV_IS_IN_DATAFLASH
174 #ifdef CFG_ENV_IS_IN_DATAFLASH
175 #define CFG_ENV_OFFSET 0x20000
176 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
177 #define CFG_ENV_SIZE 0x2000 /* 0x8000 */
179 #define CFG_ENV_IS_IN_FLASH 1
180 #ifdef CONFIG_INIT_CRITICAL
181 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
182 #define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */
184 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
185 #define CFG_ENV_SIZE 0x2000 /* 0x8000 */
186 #endif /* CONFIG_INIT_CRITICAL */
187 #endif /* CFG_ENV_IS_IN_DATAFLASH */
190 #define CFG_LOAD_ADDR 0x21000000 /* default load address */
192 #ifdef CONFIG_INIT_CRITICAL
193 #define CFG_BOOT_SIZE 0x00 /* 0 KBytes */
194 #define CFG_U_BOOT_BASE PHYS_FLASH_1
195 #define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */
197 #define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */
198 #define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
199 #define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */
200 #endif /* CONFIG_INIT_CRITICAL */
202 #define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
204 #define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
205 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
206 #define CFG_MAXARGS 16 /* max number of command args */
207 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
210 /*-----------------------------------------------------------------------
211 * Board specific extension for bd_info
213 * This structure is embedded in the global bd_info (bd_t) structure
214 * and can be used by the board specific code (eg board/...)
218 /* helper variable for board environment handling
220 * env_crc_valid == 0 => uninitialised
221 * env_crc_valid > 0 => environment crc in flash is valid
222 * env_crc_valid < 0 => environment crc in flash is invalid
229 #define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
230 /* AT91C_TC_TIMER_DIV1_CLOCK */
232 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
234 #ifdef CONFIG_USE_IRQ
235 #error CONFIG_USE_IRQ not supported