2 * Copyright (C) 2006 Atmel Corporation
4 * Configuration settings for the AVR32 Network Gateway
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/hardware.h>
14 #define CONFIG_AT32AP7000
15 #define CONFIG_ATNGW100
18 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
19 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
20 * and the PBA bus to run at 1/4 the PLL frequency.
23 #define CONFIG_SYS_POWER_MANAGER
24 #define CONFIG_SYS_OSC0_HZ 20000000
25 #define CONFIG_SYS_PLL0_DIV 1
26 #define CONFIG_SYS_PLL0_MUL 7
27 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
28 #define CONFIG_SYS_CLKDIV_CPU 0
29 #define CONFIG_SYS_CLKDIV_HSB 1
30 #define CONFIG_SYS_CLKDIV_PBA 2
31 #define CONFIG_SYS_CLKDIV_PBB 1
33 /* Reserve VM regions for SDRAM and NOR flash */
34 #define CONFIG_SYS_NR_VM_REGIONS 2
37 * The PLLOPT register controls the PLL like this:
41 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
43 #define CONFIG_SYS_PLL0_OPT 0x04
45 #define CONFIG_USART_BASE ATMEL_BASE_USART1
46 #define CONFIG_USART_ID 1
47 /* User serviceable stuff */
48 #define CONFIG_DOS_PARTITION
50 #define CONFIG_CMDLINE_TAG
51 #define CONFIG_SETUP_MEMORY_TAGS
52 #define CONFIG_INITRD_TAG
54 #define CONFIG_STACKSIZE (2048)
56 #define CONFIG_BAUDRATE 115200
57 #define CONFIG_BOOTARGS \
58 "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
59 #define CONFIG_BOOTCOMMAND \
62 #define CONFIG_BOOTDELAY 1
65 * After booting the board for the first time, new ethernet addresses
66 * should be generated and assigned to the environment variables
67 * "ethaddr" and "eth1addr". This is normally done during production.
69 #define CONFIG_OVERWRITE_ETHADDR_ONCE
74 #define CONFIG_BOOTP_SUBNETMASK
75 #define CONFIG_BOOTP_GATEWAY
78 * Command line configuration.
80 #include <config_cmd_default.h>
82 #define CONFIG_CMD_ASKENV
83 #define CONFIG_CMD_DHCP
84 #define CONFIG_CMD_EXT2
85 #define CONFIG_CMD_FAT
86 #define CONFIG_CMD_JFFS2
87 #define CONFIG_CMD_MMC
89 #define CONFIG_CMD_SPI
91 #undef CONFIG_CMD_FPGA
92 #undef CONFIG_CMD_SETGETDCR
93 #undef CONFIG_CMD_SOURCE
94 #undef CONFIG_CMD_XIMG
96 #define CONFIG_ATMEL_USART
98 #define CONFIG_PORTMUX_PIO
99 #define CONFIG_SYS_NR_PIOS 5
100 #define CONFIG_SYS_HSDRAMC
102 #define CONFIG_GENERIC_ATMEL_MCI
103 #define CONFIG_GENERIC_MMC
104 #define CONFIG_ATMEL_SPI
106 #define CONFIG_SPI_FLASH
107 #define CONFIG_SPI_FLASH_ATMEL
109 #define CONFIG_SYS_DCACHE_LINESZ 32
110 #define CONFIG_SYS_ICACHE_LINESZ 32
112 #define CONFIG_NR_DRAM_BANKS 1
114 #define CONFIG_SYS_FLASH_CFI
115 #define CONFIG_FLASH_CFI_DRIVER
117 #define CONFIG_SYS_FLASH_BASE 0x00000000
118 #define CONFIG_SYS_FLASH_SIZE 0x800000
119 #define CONFIG_SYS_MAX_FLASH_BANKS 1
120 #define CONFIG_SYS_MAX_FLASH_SECT 135
122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
123 #define CONFIG_SYS_TEXT_BASE 0x00000000
125 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
126 #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
127 #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
129 #define CONFIG_ENV_IS_IN_FLASH
130 #define CONFIG_ENV_SIZE 65536
131 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
133 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
135 #define CONFIG_SYS_MALLOC_LEN (256*1024)
137 /* Allow 4MB for the kernel run-time image */
138 #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
139 #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
141 /* Other configuration settings that shouldn't have to change all that often */
142 #define CONFIG_SYS_PROMPT "U-Boot> "
143 #define CONFIG_SYS_CBSIZE 256
144 #define CONFIG_SYS_MAXARGS 16
145 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
146 #define CONFIG_SYS_LONGHELP
148 #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
149 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
151 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
153 #endif /* __CONFIG_H */