2 * Copyright (C) 2006 Atmel Corporation
4 * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
6 * Configuration settings for the AVR32 Network Gateway
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/hardware.h>
16 #define CONFIG_AT32AP7000
17 #define CONFIG_ATNGW100MKII
19 #define CONFIG_BOARD_EARLY_INIT_R
22 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
23 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
24 * and the PBA bus to run at 1/4 the PLL frequency.
27 #define CONFIG_SYS_POWER_MANAGER
28 #define CONFIG_SYS_OSC0_HZ 20000000
29 #define CONFIG_SYS_PLL0_DIV 1
30 #define CONFIG_SYS_PLL0_MUL 7
31 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
33 * Set the CPU running at:
34 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
36 #define CONFIG_SYS_CLKDIV_CPU 0
38 * Set the HSB running at:
39 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
41 #define CONFIG_SYS_CLKDIV_HSB 1
43 * Set the PBA running at:
44 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
46 #define CONFIG_SYS_CLKDIV_PBA 2
48 * Set the PBB running at:
49 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
51 #define CONFIG_SYS_CLKDIV_PBB 1
53 /* Reserve VM regions for NOR flash, NAND flash and SDRAM */
54 #define CONFIG_SYS_NR_VM_REGIONS 3
57 * The PLLOPT register controls the PLL like this:
61 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
63 #define CONFIG_SYS_PLL0_OPT 0x04
65 #define CONFIG_USART_BASE ATMEL_BASE_USART1
66 #define CONFIG_USART_ID 1
68 /* User serviceable stuff */
70 #define CONFIG_CMDLINE_TAG
71 #define CONFIG_SETUP_MEMORY_TAGS
72 #define CONFIG_INITRD_TAG
74 #define CONFIG_STACKSIZE (2048)
76 #define CONFIG_BOOTARGS \
77 "root=mtd:main rootfstype=jffs2"
78 #define CONFIG_BOOTCOMMAND \
79 "fsload 0x10400000 /uImage; bootm"
83 * After booting the board for the first time, new ethernet addresses
84 * should be generated and assigned to the environment variables
85 * "ethaddr" and "eth1addr". This is normally done during production.
87 #define CONFIG_OVERWRITE_ETHADDR_ONCE
92 #define CONFIG_BOOTP_SUBNETMASK
93 #define CONFIG_BOOTP_GATEWAY
96 * Command line configuration.
98 #define CONFIG_CMD_JFFS2
100 #define CONFIG_ATMEL_USART
102 #define CONFIG_PORTMUX_PIO
103 #define CONFIG_SYS_NR_PIOS 5
104 #define CONFIG_SYS_HSDRAMC
105 #define CONFIG_GENERIC_ATMEL_MCI
106 #define CONFIG_ATMEL_SPI
108 #define CONFIG_SYS_DCACHE_LINESZ 32
109 #define CONFIG_SYS_ICACHE_LINESZ 32
111 #define CONFIG_NR_DRAM_BANKS 1
113 #define CONFIG_SYS_FLASH_CFI
114 #define CONFIG_FLASH_CFI_DRIVER
115 #define CONFIG_SYS_FLASH_PROTECTION
117 #define CONFIG_SYS_FLASH_BASE 0x00000000
118 #define CONFIG_SYS_FLASH_SIZE 0x800000
119 #define CONFIG_SYS_MAX_FLASH_BANKS 1
120 #define CONFIG_SYS_MAX_FLASH_SECT 135
122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
123 #define CONFIG_SYS_TEXT_BASE 0x00000000
125 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
126 #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
127 #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
129 #define CONFIG_ENV_IS_IN_FLASH
130 #define CONFIG_ENV_SIZE 65536
131 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
133 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
135 #define CONFIG_SYS_MALLOC_LEN (256*1024)
137 /* Allow 4MB for the kernel run-time image */
138 #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
139 #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
141 /* Other configuration settings that shouldn't have to change all that often */
142 #define CONFIG_SYS_CBSIZE 256
143 #define CONFIG_SYS_MAXARGS 16
144 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
145 #define CONFIG_SYS_LONGHELP
147 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
148 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
150 #define CONFIG_MTD_DEVICE
151 #define CONFIG_MTD_PARTITIONS
153 #endif /* __CONFIG_H */