2 * Copyright (C) 2005-2006 Atmel Corporation
4 * Configuration settings for the ATSTK1002 CPU daughterboard
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #define CONFIG_AVR32 1
28 #define CONFIG_AT32AP 1
29 #define CONFIG_AT32AP7000 1
30 #define CONFIG_ATSTK1002 1
31 #define CONFIG_ATSTK1000 1
33 #define CONFIG_ATSTK1000_EXT_FLASH 1
36 * Timer clock frequency. We're using the CPU-internal COUNT register
37 * for this, so this is equivalent to the CPU core clock frequency
42 * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
43 * frequency and the peripherals to run at 1/4 the PLL frequency.
46 #define CFG_POWER_MANAGER 1
47 #define CFG_OSC0_HZ 20000000
48 #define CFG_PLL0_DIV 1
49 #define CFG_PLL0_MUL 7
50 #define CFG_PLL0_SUPPRESS_CYCLES 16
51 #define CFG_CLKDIV_CPU 0
52 #define CFG_CLKDIV_HSB 1
53 #define CFG_CLKDIV_PBA 2
54 #define CFG_CLKDIV_PBB 1
57 * The PLLOPT register controls the PLL like this:
61 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
63 #define CFG_PLL0_OPT 0x04
66 #define CONFIG_USART1 1
70 /* User serviceable stuff */
71 #define CONFIG_CMDLINE_TAG 1
72 #define CONFIG_SETUP_MEMORY_TAGS 1
73 #define CONFIG_INITRD_TAG 1
75 #define CONFIG_STACKSIZE (2048)
77 #define CONFIG_BAUDRATE 115200
78 #define CONFIG_BOOTARGS \
79 "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k"
81 #define CONFIG_BOOTCOMMAND \
82 "fsload; bootm $(fileaddr)"
85 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
86 * data on the serial line may interrupt the boot sequence.
88 #define CONFIG_BOOTDELAY 2
89 #define CONFIG_AUTOBOOT 1
90 #define CONFIG_AUTOBOOT_KEYED 1
91 #define CONFIG_AUTOBOOT_PROMPT \
92 "Press SPACE to abort autoboot in %d seconds\n"
93 #define CONFIG_AUTOBOOT_DELAY_STR "d"
94 #define CONFIG_AUTOBOOT_STOP_STR " "
96 #define CONFIG_COMMANDS (CFG_CMD_BDI \
100 /* | CFG_CMD_CACHE */ \
103 /* | CFG_CMD_NET */ \
105 /* | CFG_CMD_IRQ */ \
108 /* | CFG_CMD_EEPROM */ \
112 /* | CFG_CMD_I2C */ \
114 /* | CFG_CMD_DATE */ \
115 /* | CFG_CMD_DHCP */ \
116 /* | CFG_CMD_AUTOSCRIPT */ \
117 /* | CFG_CMD_MII */ \
119 /* | CFG_CMD_SDRAM */ \
120 /* | CFG_CMD_DIAG */ \
121 /* | CFG_CMD_HWFLOW */ \
122 /* | CFG_CMD_SAVES */ \
123 /* | CFG_CMD_SPI */ \
124 /* | CFG_CMD_PING */ \
125 /* | CFG_CMD_MMC */ \
126 /* | CFG_CMD_FAT */ \
128 /* | CFG_CMD_ITEST */ \
129 /* | CFG_CMD_EXT2 */ \
133 #include <cmd_confdefs.h>
135 #define CONFIG_ATMEL_USART 1
136 #define CONFIG_PIO2 1
137 #define CFG_NR_PIOS 5
138 #define CFG_HSDRAMC 1
140 #define CFG_DCACHE_LINESZ 32
141 #define CFG_ICACHE_LINESZ 32
143 #define CONFIG_NR_DRAM_BANKS 1
145 /* External flash on STK1000 */
147 #define CFG_FLASH_CFI 1
148 #define CFG_FLASH_CFI_DRIVER 1
151 #define CFG_FLASH_BASE 0x00000000
152 #define CFG_FLASH_SIZE 0x800000
153 #define CFG_MAX_FLASH_BANKS 1
154 #define CFG_MAX_FLASH_SECT 135
156 #define CFG_MONITOR_BASE CFG_FLASH_BASE
158 #define CFG_INTRAM_BASE 0x24000000
159 #define CFG_INTRAM_SIZE 0x8000
161 #define CFG_SDRAM_BASE 0x10000000
163 #define CFG_ENV_IS_IN_FLASH 1
164 #define CFG_ENV_SIZE 65536
165 #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
167 #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
169 #define CFG_MALLOC_LEN (256*1024)
170 #define CFG_DMA_ALLOC_LEN (16384)
172 /* Allow 2MB for the kernel run-time image */
173 #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
174 #define CFG_BOOTPARAMS_LEN (16 * 1024)
176 /* Other configuration settings that shouldn't have to change all that often */
177 #define CFG_PROMPT "Uboot> "
178 #define CFG_CBSIZE 256
179 #define CFG_MAXARGS 8
180 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
181 #define CFG_LONGHELP 1
183 #define CFG_MEMTEST_START \
184 ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
185 #define CFG_MEMTEST_END \
187 DECLARE_GLOBAL_DATA_PTR; \
188 gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
190 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
192 #endif /* __CONFIG_H */