3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /************************************************************************
25 * bamboo.h - configuration for BAMBOO board
26 ***********************************************************************/
30 /*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
33 #define CONFIG_BAMBOO 1 /* Board is BAMBOO */
34 #define CONFIG_440_EP 1 /* Specific PPC440EP support */
36 #define CONFIG_4xx 1 /* ... PPC4xx family */
37 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
38 #undef CFG_DRAM_TEST /* disable - takes long time! */
39 //#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
40 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
42 /*-----------------------------------------------------------------------
43 * Base addresses -- Note these are effective addresses where the
44 * actual resources get mapped (not physical addresses)
45 *----------------------------------------------------------------------*/
46 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
47 #define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
48 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
49 #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
50 #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
51 #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
52 #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
55 /*Don't change either of these*/
56 #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
57 #define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
58 /*Don't change either of these*/
60 #define CFG_USB_DEVICE 0x50000000
61 #define CFG_NVRAM_BASE_ADDR 0x80000000
62 #define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
64 /*-----------------------------------------------------------------------
65 * Initial RAM & stack pointer (placed in SDRAM)
66 *----------------------------------------------------------------------*/
67 #define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
68 #define CFG_INIT_RAM_END 0x2000
69 #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
70 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
71 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
73 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
74 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
75 #define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
76 //#define CFG_SDRAM_BANKS (2)
77 #define CFG_SDRAM_BANKS (1)
79 /*-----------------------------------------------------------------------
81 *----------------------------------------------------------------------*/
82 #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
83 #define CONFIG_BAUDRATE 115200
84 #define CONFIG_SERIAL_MULTI 1
85 /*define this if you want console on UART1*/
86 #undef CONFIG_UART1_CONSOLE
88 #define CFG_BAUDRATE_TABLE \
89 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
91 /*-----------------------------------------------------------------------
94 * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
95 * The DS1558 code assumes this condition
97 *----------------------------------------------------------------------*/
98 #define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
99 #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
101 /*-----------------------------------------------------------------------
103 *----------------------------------------------------------------------*/
104 #if 0 /* test-only */
105 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
106 #define CFG_MAX_FLASH_SECT 256 /* sectors per device */
108 #undef CFG_FLASH_CHECKSUM
109 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
110 #define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
112 #define CFG_FLASH_CFI /* The flash is CFI compatible */
113 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
114 #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
116 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
117 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
119 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
120 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
122 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
125 /*-----------------------------------------------------------------------
127 *----------------------------------------------------------------------*/
128 #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
130 /*-----------------------------------------------------------------------
132 *----------------------------------------------------------------------*/
133 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
134 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
135 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
136 #define CFG_I2C_SLAVE 0x7F
139 /*-----------------------------------------------------------------------
141 *----------------------------------------------------------------------*/
142 #undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
143 #undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
144 #define CFG_ENV_IS_IN_EEPROM 1
146 /* Define to allow the user to overwrite serial and ethaddr */
147 #define CONFIG_ENV_OVERWRITE
149 #define CFG_I2C_MULTI_EEPROMS
150 #define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
151 #define CFG_ENV_OFFSET 0x0
152 #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
153 #define CFG_I2C_EEPROM_ADDR_LEN 1
154 #define CFG_EEPROM_PAGE_WRITE_ENABLE
155 #define CFG_EEPROM_PAGE_WRITE_BITS 3
156 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
158 #define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
159 #define CONFIG_BOOTDELAY 3 /* disable autoboot */
161 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
162 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
164 #define CONFIG_MII 1 /* MII PHY management */
165 #define CONFIG_NET_MULTI 1 /* required for netconsole */
166 #define CONFIG_PHY1_ADDR 3
167 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
168 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
169 #define CONFIG_NETMASK 255.255.255.0
170 #define CONFIG_IPADDR 10.0.4.251
171 #define CONFIG_ETHADDR 00:10:EC:00:12:34
172 #define CONFIG_ETH1ADDR 00:10:EC:00:12:35
174 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
175 #define CONFIG_SERVERIP 10.0.4.115
178 #define CONFIG_MAC_PARTITION
179 #define CONFIG_DOS_PARTITION
180 #define CONFIG_ISO_PARTITION
184 #define CONFIG_USB_OHCI
185 #define CONFIG_USB_STORAGE
187 /*Comment this out to enable USB 1.1 device*/
188 #define USB_2_0_DEVICE
189 #endif /*CONFIG_440_EP*/
192 #define CONFIG_PANIC_HANG
194 #define CONFIG_HW_WATCHDOG /* watchdog */
198 /* Need to define POST */
199 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
206 /* CFG_CMD_EXT2 |*/ \
211 /* CFG_CMD_KGDB |*/ \
222 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
229 /* CFG_CMD_EXT2 |*/ \
234 /* CFG_CMD_KGDB |*/ \
245 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
246 #include <cmd_confdefs.h>
249 * Miscellaneous configurable options
251 #define CFG_LONGHELP /* undef to save memory */
252 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
253 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
254 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
256 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
258 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
259 #define CFG_MAXARGS 16 /* max number of command args */
260 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
262 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
263 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
265 #define CFG_LOAD_ADDR 0x100000 /* default load address */
266 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
267 #define CONFIG_LYNXKDI 1 /* support kdi files */
269 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
271 /*-----------------------------------------------------------------------
273 *-----------------------------------------------------------------------
276 #define CONFIG_PCI /* include pci support */
277 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
278 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
279 #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
281 /* Board-specific PCI */
282 #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
283 #define CFG_PCI_TARGET_INIT
284 #define CFG_PCI_MASTER_INIT
286 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
287 #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
290 * For booting Linux, the board info and command line data
291 * have to be in the first 8 MB of memory, since this is
292 * the maximum mapped by the Linux kernel during initialization.
294 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
295 /*-----------------------------------------------------------------------
296 * Cache Configuration
298 #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
299 #define CFG_CACHELINE_SIZE 32 /* ... */
300 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
301 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
305 * Internal Definitions
309 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
310 #define BOOTFLAG_WARM 0x02 /* Software reboot */
312 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
313 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
314 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
316 #endif /* __CONFIG_H */