2 * U-boot - Configuration file for BF533 STAMP board
5 #ifndef __CONFIG_BF533_STAMP_H__
6 #define __CONFIG_BF533_STAMP_H__
8 #include <asm/config-pre.h>
14 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 /* CONFIG_CLKIN_HZ is any value in Hz */
23 #define CONFIG_CLKIN_HZ 11059200
24 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26 #define CONFIG_CLKIN_HALF 0
27 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29 #define CONFIG_PLL_BYPASS 0
30 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
31 /* Values can range from 0-63 (where 0 means 64) */
32 #define CONFIG_VCO_MULT 45
33 /* CCLK_DIV controls the core clock divider */
34 /* Values can be 1, 2, 4, or 8 ONLY */
35 #define CONFIG_CCLK_DIV 1
36 /* SCLK_DIV controls the system clock divider */
37 /* Values can range from 1-15 */
38 #define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
44 #define CONFIG_MEM_ADD_WDTH 11
45 #define CONFIG_MEM_SIZE 128
47 #define CONFIG_EBIU_SDRRC_VAL 0x268
48 #define CONFIG_EBIU_SDGCTL_VAL 0x911109
50 #define CONFIG_EBIU_AMGCTL_VAL 0xFF
51 #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
52 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
54 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
55 #define CONFIG_SYS_MALLOC_LEN (384 * 1024)
61 #define ADI_CMDS_NETWORK 1
62 #define CONFIG_NET_MULTI
63 #define CONFIG_SMC91111 1
64 #define CONFIG_SMC91111_BASE 0x20300300
65 #define SMC91111_EEPROM_INIT() \
67 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
68 bfin_write_FIO_FLAG_C(PF1); \
69 bfin_write_FIO_FLAG_S(PF0); \
72 #define CONFIG_HOSTNAME bf533-stamp
73 /* Uncomment next line to use fixed MAC address */
74 /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
80 #define CONFIG_FLASH_CFI_DRIVER
81 #define CONFIG_SYS_FLASH_BASE 0x20000000
82 #define CONFIG_SYS_FLASH_CFI
83 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
84 #define CONFIG_SYS_MAX_FLASH_BANKS 1
85 #define CONFIG_SYS_MAX_FLASH_SECT 67
91 #define CONFIG_BFIN_SPI
92 #define CONFIG_ENV_SPI_MAX_HZ 30000000
93 #define CONFIG_SF_DEFAULT_SPEED 30000000
94 #define CONFIG_SPI_FLASH
95 #define CONFIG_SPI_FLASH_ATMEL
96 #define CONFIG_SPI_FLASH_SPANSION
97 #define CONFIG_SPI_FLASH_STMICRO
98 #define CONFIG_SPI_FLASH_WINBOND
102 * Env Storage Settings
104 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
105 #define CONFIG_ENV_IS_IN_SPI_FLASH
106 #define CONFIG_ENV_OFFSET 0x10000
107 #define CONFIG_ENV_SIZE 0x2000
108 #define CONFIG_ENV_SECT_SIZE 0x10000
110 #define CONFIG_ENV_IS_IN_FLASH
111 #define CONFIG_ENV_OFFSET 0x4000
112 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
113 #define CONFIG_ENV_SIZE 0x2000
114 #define CONFIG_ENV_SECT_SIZE 0x2000
116 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
117 #define ENV_IS_EMBEDDED
119 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR
121 #ifdef ENV_IS_EMBEDDED
122 /* WARNING - the following is hand-optimized to fit within
123 * the sector before the environment sector. If it throws
124 * an error during compilation remove an object here to get
125 * it linked after the configuration sector.
127 # define LDS_BOARD_TEXT \
128 arch/blackfin/cpu/traps.o (.text .text.*); \
129 arch/blackfin/cpu/interrupt.o (.text .text.*); \
130 arch/blackfin/cpu/serial.o (.text .text.*); \
131 common/dlmalloc.o (.text .text.*); \
132 lib/crc32.o (.text .text.*); \
133 . = DEFINED(env_offset) ? env_offset : .; \
134 common/env_embedded.o (.text .text.*);
141 #define CONFIG_SOFT_I2C
142 #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
143 #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
147 * Compact Flash / IDE / ATA Settings
150 /* Enabled below option for CF support */
151 /* #define CONFIG_STAMP_CF */
152 #if defined(CONFIG_STAMP_CF)
153 #define CONFIG_MISC_INIT_R
154 #define CONFIG_DOS_PARTITION 1
155 #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
156 #undef CONFIG_IDE_LED /* no led for ide supported */
157 #undef CONFIG_IDE_RESET /* no reset for ide supported */
159 #define CONFIG_SYS_IDE_MAXBUS 1
160 #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
162 #define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
163 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
165 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
166 #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
167 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
169 #define CONFIG_SYS_ATA_STRIDE 2
171 #undef CONFIG_EBIU_AMBCTL1_VAL
172 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
179 #define CONFIG_RTC_BFIN
180 #define CONFIG_UART_CONSOLE 0
182 /* FLASH/ETHERNET uses the same async bank */
183 #define SHARED_RESOURCES 1
185 /* define to enable boot progress via leds */
186 /* #define CONFIG_SHOW_BOOT_PROGRESS */
188 /* define to enable run status via led */
189 /* #define CONFIG_STATUS_LED */
190 #ifdef CONFIG_STATUS_LED
191 #define CONFIG_GPIO_LED
192 #define CONFIG_BOARD_SPECIFIC_LED
193 /* use LED0 to indicate booting/alive */
194 #define STATUS_LED_BOOT 0
195 #define STATUS_LED_BIT GPIO_PF2
196 #define STATUS_LED_STATE STATUS_LED_ON
197 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
198 /* use LED1 to indicate crash */
199 #define STATUS_LED_CRASH 1
200 #define STATUS_LED_BIT1 GPIO_PF3
201 #define STATUS_LED_STATE1 STATUS_LED_ON
202 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
203 /* #define STATUS_LED_BIT2 GPIO_PF4 */
206 /* define to enable splash screen support */
207 /* #define CONFIG_VIDEO */
211 * Pull in common ADI header for remaining command/environment setup
213 #include <configs/bfin_adi_common.h>