2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC855 1 /* This is a MPC855 CPU */
37 #define CONFIG_C2MON 1 /* ...on a C2MON module */
39 #define CONFIG_80MHz 1 /* Running at 5 * 16 = 80 MHz */
41 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42 #undef CONFIG_8xx_CONS_SMC2
43 #undef CONFIG_8xx_CONS_NONE
44 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
46 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
48 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
51 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
53 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
55 #undef CONFIG_BOOTARGS
56 #define CONFIG_BOOTCOMMAND \
58 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
59 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
62 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
63 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
65 #undef CONFIG_WATCHDOG /* watchdog disabled */
67 #undef CONFIG_STATUS_LED /* Status LED disabled */
69 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
71 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
73 #define CONFIG_MAC_PARTITION
74 #define CONFIG_DOS_PARTITION
76 #define CONFIG_FEC_ENET 1 /* Use Fast Ethernet Controller */
78 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
82 * Command line configuration.
84 #include <config_cmd_default.h>
86 #define CONFIG_CMD_DATE
87 #define CONFIG_CMD_DHCP
88 #define CONFIG_CMD_IDE
89 #define CONFIG_CMD_NFS
90 #define CONFIG_CMD_SNTP
94 * Miscellaneous configurable options
96 #define CFG_LONGHELP /* undef to save memory */
97 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
99 #undef CFG_HUSH_PARSER /* use "hush" command parser */
100 #ifdef CFG_HUSH_PARSER
101 #define CFG_PROMPT_HUSH_PS2 "> "
104 #if defined(CONFIG_CMD_KGDB)
105 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
107 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
109 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
110 #define CFG_MAXARGS 16 /* max number of command args */
111 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
113 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
114 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
116 #define CFG_LOAD_ADDR 0x100000 /* default load address */
118 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
120 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
123 * Low Level Configuration Settings
124 * (address mappings, register initial values, etc.)
125 * You should know what you are doing if you make changes here.
127 /*-----------------------------------------------------------------------
128 * Internal Memory Mapped Register
130 #define CFG_IMMR 0xFFF00000
132 /*-----------------------------------------------------------------------
133 * Definitions for initial stack pointer and data area (in DPRAM)
135 #define CFG_INIT_RAM_ADDR CFG_IMMR
136 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
137 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
138 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
139 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
141 /*-----------------------------------------------------------------------
142 * Start addresses for the final memory configuration
143 * (Set up by the startup code)
144 * Please note that CFG_SDRAM_BASE _must_ start at 0
146 #define CFG_SDRAM_BASE 0x00000000
147 #define CFG_FLASH_BASE 0x40000000
149 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
151 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
153 #define CFG_MONITOR_BASE CFG_FLASH_BASE
154 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
157 * For booting Linux, the board info and command line data
158 * have to be in the first 8 MB of memory, since this is
159 * the maximum mapped by the Linux kernel during initialization.
161 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
163 /*-----------------------------------------------------------------------
166 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
167 #define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
169 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
170 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
172 #define CFG_ENV_IS_IN_FLASH 1
173 #define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
174 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
176 /*-----------------------------------------------------------------------
177 * Cache Configuration
179 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
180 #if defined(CONFIG_CMD_KGDB)
181 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
184 /*-----------------------------------------------------------------------
185 * SYPCR - System Protection Control 11-9
186 * SYPCR can only be written once after reset!
187 *-----------------------------------------------------------------------
188 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
190 #if defined(CONFIG_WATCHDOG)
191 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
192 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
194 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
197 /*-----------------------------------------------------------------------
198 * SIUMCR - SIU Module Configuration 11-6
199 *-----------------------------------------------------------------------
200 * PCMCIA config., multi-function pin tri-state
202 #ifndef CONFIG_CAN_DRIVER
203 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
204 #else /* we must activate GPL5 in the SIUMCR for CAN */
205 #define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
206 #endif /* CONFIG_CAN_DRIVER */
208 /*-----------------------------------------------------------------------
209 * TBSCR - Time Base Status and Control 11-26
210 *-----------------------------------------------------------------------
211 * Clear Reference Interrupt Status, Timebase freezing enabled
213 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
215 /*-----------------------------------------------------------------------
216 * RTCSC - Real-Time Clock Status and Control Register 11-27
217 *-----------------------------------------------------------------------
219 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
221 /*-----------------------------------------------------------------------
222 * PISCR - Periodic Interrupt Status and Control 11-31
223 *-----------------------------------------------------------------------
224 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
226 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
228 /*-----------------------------------------------------------------------
229 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
230 *-----------------------------------------------------------------------
231 * Reset PLL lock status sticky bit, timer expired status bit and timer
232 * interrupt status bit
234 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
236 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
238 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
239 #else /* up to 50 MHz we use a 1:1 clock */
240 #define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
241 #endif /* CONFIG_80MHz */
243 /*-----------------------------------------------------------------------
244 * SCCR - System Clock and reset Control Register 15-27
245 *-----------------------------------------------------------------------
246 * Set clock output, timebase and RTC source and divider,
247 * power management and some other internal clocks
249 #define SCCR_MASK SCCR_EBDF11
250 #ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
251 #define CFG_SCCR (/* SCCR_TBS | */ \
252 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
253 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
255 #else /* up to 50 MHz we use a 1:1 clock */
256 #define CFG_SCCR (SCCR_TBS | \
257 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
258 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
260 #endif /* CONFIG_80MHz */
262 /*-----------------------------------------------------------------------
264 *-----------------------------------------------------------------------
267 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
268 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
269 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
270 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
271 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
272 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
273 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
274 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
276 /*-----------------------------------------------------------------------
277 * PCMCIA Power Switch
279 * The C2MON uses a TPS2211A PC-Card Power-Interface Switch to
280 * control the voltages on the PCMCIA slot which is connected
281 * to Port C (all outputs) and Port B (Over-Current Input)
282 *-----------------------------------------------------------------------
285 #define TPS2211_VCCD0 0x0002 /* PC.14 */
286 #define TPS2211_VCCD1 0x0004 /* PC.13 */
287 #define TPS2211_VPPD0 0x0008 /* PC.12 */
288 #define TPS2211_VPPD1 0x0010 /* PC.11 */
289 #define TPS2211_OUTPUTS ( TPS2211_VCCD0 | TPS2211_VCCD1 | \
290 TPS2211_VPPD0 | TPS2211_VPPD1 )
293 #define TPS2211_OC 0x00000200 /* PB.22: Over-Current */
294 #define TPS2211_INPUTS ( TPS2211_OC )
296 /*-----------------------------------------------------------------------
297 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
298 *-----------------------------------------------------------------------
301 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
303 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
304 #undef CONFIG_IDE_LED /* LED for ide not supported */
305 #undef CONFIG_IDE_RESET /* reset for ide not supported */
307 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
308 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
310 #define CFG_ATA_IDE0_OFFSET 0x0000
312 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
314 /* Offset for data I/O */
315 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
317 /* Offset for normal register accesses */
318 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
320 /* Offset for alternate registers */
321 #define CFG_ATA_ALT_OFFSET 0x0100
324 /*-----------------------------------------------------------------------
326 *-----------------------------------------------------------------------
332 * Init Memory Controller:
334 * BR0/1 and OR0/1 (FLASH)
337 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
338 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
340 /* used to re-map FLASH both when starting from SRAM or FLASH:
341 * restrict access enough to keep SRAM working (if any)
342 * but not too much to meddle with FLASH accesses
344 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
345 #define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
347 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
348 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
349 OR_SCY_5_CLK | OR_EHTR)
351 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
352 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
353 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
355 #define CFG_OR1_REMAP CFG_OR0_REMAP
356 #define CFG_OR1_PRELIM CFG_OR0_PRELIM
357 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
360 * BR2/3 and OR2/3 (SDRAM)
363 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
364 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
365 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
367 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
368 #define CFG_OR_TIMING_SDRAM 0x00000A00
370 #define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
371 #define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
373 #ifndef CONFIG_CAN_DRIVER
374 #define CFG_OR3_PRELIM CFG_OR2_PRELIM
375 #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
376 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
377 #define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
378 #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
379 #define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
380 #define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
381 BR_PS_8 | BR_MS_UPMB | BR_V )
382 #endif /* CONFIG_CAN_DRIVER */
385 * Memory Periodic Timer Prescaler
388 /* periodic timer for refresh */
389 #define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
391 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
392 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
393 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
395 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
396 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
397 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
400 * MAMR settings for SDRAM
404 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
405 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
406 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
408 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
409 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
410 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
414 * Internal Definitions
418 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
419 #define BOOTFLAG_WARM 0x02 /* Software reboot */
421 #endif /* __CONFIG_H */