2 * Copyright (C) 2009 Texas Instruments Incorporated
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
27 #define CONFIG_SYS_CONSOLE_INFO_QUIET
29 /* SoC Configuration */
30 #define CONFIG_ARM926EJS /* arm926ejs CPU */
31 #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
32 #define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
33 #define CONFIG_SYS_HZ 1000
34 #define CONFIG_SOC_DM365
36 #define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
38 #define CONFIG_HOSTNAME cam_enc_4xx
40 #define CONFIG_BOARD_LATE_INIT
41 #define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
44 #define CONFIG_NR_DRAM_BANKS 1
45 #define PHYS_SDRAM_1 0x80000000
46 #define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
47 #define DDR_4BANKS /* 4-bank DDR2 (256MB) */
48 #define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
49 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
51 /* Serial Driver info: UART0 for console */
52 #define CONFIG_SYS_NS16550
53 #define CONFIG_SYS_NS16550_SERIAL
54 #define CONFIG_SYS_NS16550_REG_SIZE -4
55 #define CONFIG_SYS_NS16550_COM1 0x01c20000
56 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
57 #define CONFIG_CONS_INDEX 1
58 #define CONFIG_BAUDRATE 115200
60 /* Network Configuration */
61 #define CONFIG_DRIVER_TI_EMAC
62 #define CONFIG_EMAC_MDIO_PHY_NUM 0
63 #define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
65 #define CONFIG_BOOTP_DEFAULT
66 #define CONFIG_BOOTP_DNS
67 #define CONFIG_BOOTP_DNS2
68 #define CONFIG_BOOTP_SEND_HOSTNAME
69 #define CONFIG_NET_RETRY_COUNT 10
70 #define CONFIG_CMD_MII
71 #define CONFIG_SYS_DCACHE_OFF
72 #define CONFIG_RESET_PHY_R
75 #define CONFIG_HARD_I2C
76 #define CONFIG_DRIVER_DAVINCI_I2C
77 #define CONFIG_SYS_I2C_SPEED 400000
78 #define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
80 /* NAND: socketed, two chipselects, normally 2 GBytes */
81 #define CONFIG_NAND_DAVINCI
82 #define CONFIG_SYS_NAND_CS 2
83 #define CONFIG_SYS_NAND_USE_FLASH_BBT
84 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
85 #define CONFIG_SYS_NAND_PAGE_2K
87 #define CONFIG_SYS_NAND_LARGEPAGE
88 #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
89 /* socket has two chipselects, nCE0 gated by address BIT(14) */
90 #define CONFIG_SYS_MAX_NAND_DEVICE 1
94 #define CONFIG_SPI_FLASH
95 #define CONFIG_SPI_FLASH_STMICRO
96 #define CONFIG_DAVINCI_SPI
97 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
98 #define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
99 #define CONFIG_SF_DEFAULT_SPEED 3000000
100 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
101 #define CONFIG_CMD_SF
105 #define CONFIG_GENERIC_MMC
106 #define CONFIG_DAVINCI_MMC
107 #define CONFIG_MMC_MBLOCK
109 /* U-Boot command configuration */
110 #include <config_cmd_default.h>
112 #define CONFIG_CMD_BDI
113 #undef CONFIG_CMD_FLASH
114 #undef CONFIG_CMD_FPGA
115 #undef CONFIG_CMD_SETGETDCR
116 #define CONFIG_CMD_ASKENV
117 #define CONFIG_CMD_CACHE
118 #define CONFIG_CMD_DHCP
119 #define CONFIG_CMD_I2C
120 #define CONFIG_CMD_PING
121 #define CONFIG_CMD_SAVES
123 #ifdef CONFIG_CMD_BDI
124 #define CONFIG_CLOCKS
128 #define CONFIG_DOS_PARTITION
129 #define CONFIG_CMD_EXT2
130 #define CONFIG_CMD_FAT
131 #define CONFIG_CMD_MMC
134 #ifdef CONFIG_NAND_DAVINCI
135 #define CONFIG_CMD_MTDPARTS
136 #define CONFIG_MTD_PARTITIONS
137 #define CONFIG_MTD_DEVICE
138 #define CONFIG_CMD_NAND
139 #define CONFIG_CMD_UBI
140 #define CONFIG_CMD_UBIFS
141 #define CONFIG_RBTREE
145 #define CONFIG_CRC32_VERIFY
146 #define CONFIG_MX_CYCLIC
148 /* U-Boot general configuration */
149 #define CONFIG_BOOTFILE "uImage" /* Boot file name */
150 #define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
151 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
152 #define CONFIG_SYS_PBSIZE /* Print buffer size */ \
153 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
154 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
155 #define CONFIG_SYS_HUSH_PARSER
156 #define CONFIG_SYS_LONGHELP
159 #define CONFIG_MENU_SHOW
161 #define CONFIG_BOARD_IMG_ADDR_R 0x80000000
163 #ifdef CONFIG_NAND_DAVINCI
164 #define CONFIG_ENV_SIZE (16 << 10)
165 #define CONFIG_ENV_IS_IN_NAND
166 #define CONFIG_ENV_OFFSET 0x180000
167 #define CONFIG_ENV_RANGE 0x040000
168 #define CONFIG_ENV_OFFSET_REDUND 0x1c0000
169 #undef CONFIG_ENV_IS_IN_FLASH
172 #if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
173 #define CONFIG_CMD_ENV
174 #define CONFIG_SYS_MMC_ENV_DEV 0
175 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
176 #define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
177 #define CONFIG_ENV_IS_IN_MMC
178 #undef CONFIG_ENV_IS_IN_FLASH
181 #define CONFIG_BOOTDELAY 3
183 * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
186 #define CONFIG_AIT_TIMER_TIMEOUT 0x186a00
188 #define CONFIG_CMDLINE_EDITING
189 #define CONFIG_VERSION_VARIABLE
190 #define CONFIG_TIMESTAMP
192 /* U-Boot memory configuration */
193 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
194 #define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
195 #define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
197 /* Linux interfacing */
198 #define CONFIG_CMDLINE_TAG
199 #define CONFIG_SETUP_MEMORY_TAGS
200 #define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
201 #define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
203 #define MTDIDS_DEFAULT "nand0=davinci_nand.0"
204 #define MTDPARTS_DEFAULT \
213 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
214 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
216 /* Defines for SPL */
218 #define CONFIG_SPL_FRAMEWORK
219 #define CONFIG_SPL_BOARD_INIT
220 #define CONFIG_SPL_LIBGENERIC_SUPPORT
221 #define CONFIG_SPL_NAND_SUPPORT
222 #define CONFIG_SPL_NAND_SIMPLE
223 #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
224 #define CONFIG_SPL_SERIAL_SUPPORT
225 #define CONFIG_SPL_POST_MEM_SUPPORT
226 #define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
227 #define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
229 #define CONFIG_SPL_TEXT_BASE 0x00000020 /*CONFIG_SYS_SRAM_START*/
230 #define CONFIG_SPL_MAX_SIZE 12320
232 #ifndef CONFIG_SPL_BUILD
233 #define CONFIG_SYS_TEXT_BASE 0x81080000
236 #define CONFIG_SYS_NAND_BASE 0x02000000
237 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
238 CONFIG_SYS_NAND_PAGE_SIZE)
240 #define CONFIG_SYS_NAND_ECCPOS { \
241 24, 25, 26, 27, 28, \
242 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
243 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
244 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
246 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
247 #define CONFIG_SYS_NAND_ECCSIZE 0x200
248 #define CONFIG_SYS_NAND_ECCBYTES 10
249 #define CONFIG_SYS_NAND_OOBSIZE 64
250 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
253 * RBL searches from Block n (n = 1..24)
254 * so we can define, how many UBL Headers
255 * we can write before the real spl code
257 #define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
259 #define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
260 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
263 * Post tests for memory testing
265 #define CONFIG_POST CONFIG_SYS_POST_MEMORY
266 #define _POST_WORD_ADDR 0x0
268 #define CONFIG_DISPLAY_BOARDINFO
270 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
272 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
273 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
274 #define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE 0x100000
277 #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
279 #define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
280 #define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
281 #define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
282 #define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
283 #define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
284 #define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
285 #define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
286 /* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
287 #define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
289 * POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
292 #define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
293 /* POST DIV 680/2 = 340Mhz -> VPSS */
294 #define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
295 /* POST DIV 680/9 = 75.6 Mhz -> VENC */
296 #define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
298 * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
301 #define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
302 /* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
303 #define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
304 /* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
305 #define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
307 #define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
308 /* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
309 #define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
310 #define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
311 /* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
312 #define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
313 /* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
314 #define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
317 * READ LATENCY 7 (CL + 2)
319 * CONFIG_EXT_STRBEN = 1
321 #define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
322 | DV_DDR_PHY_EXT_STRBEN \
323 | DV_DDR_PHY_PWRDNEN \
324 | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
327 * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
328 * T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
329 * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
330 * T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
331 * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
332 * T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
333 * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
334 * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
336 #define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
337 | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
338 | (4 << DV_DDR_SDTMR1_RP_SHIFT) \
339 | (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
340 | (5 << DV_DDR_SDTMR1_WR_SHIFT) \
341 | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
342 | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
343 | (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
344 | (2 << DV_DDR_SDTMR1_WTR_SHIFT))
347 * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
348 * T_XP = tCKE - 1 = 3 - 2
349 * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
350 * T_XSRD = txsrd - 1 = 200 - 1
351 * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
352 * T_CKE = tcke - 1 = 3 - 1
354 #define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
355 | (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
356 | (2 << DV_DDR_SDTMR2_XP_SHIFT) \
357 | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
358 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
359 | (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
360 | (2 << DV_DDR_SDTMR2_CKE_SHIFT))
362 /* PR_OLD_COUNT = 0xfe */
363 #define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
364 /* refresh rate = 0x768 */
365 #define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
367 #define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
368 | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
369 | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
370 | (5 << DV_DDR_SDCR_CL_SHIFT) \
371 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
372 | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
373 | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
374 | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
375 | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
376 | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
377 | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
379 #define CONFIG_SYS_DM36x_AWCCR 0xff
380 #define CONFIG_SYS_DM36x_AB1CR 0x40400204
381 #define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
383 /* All Video Inputs */
384 #define CONFIG_SYS_DM36x_PINMUX0 0x00000000
387 * GPIO 86, 87 + 90 0x0000f030
389 #define CONFIG_SYS_DM36x_PINMUX1 0x00530002
390 #define CONFIG_SYS_DM36x_PINMUX2 0x00001815
392 * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
395 #define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
397 * MMC/SD0 instead of MS, SPI0
400 #define CONFIG_SYS_DM36x_PINMUX4 0x00002655
403 * Default environment settings
405 #define xstr(s) str(s)
408 #define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
409 /* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
410 #define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
412 * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
413 * CONFIG_SYS_NAND_PAGE_SIZE))
415 #define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
417 #define CONFIG_EXTRA_ENV_SETTINGS \
418 "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
419 "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
420 "load=tftp ${u_boot_addr_r} ${u-boot}\0" \
421 "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
422 "writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \
423 "nand write ${u_boot_addr_r} 20000 ${pagesz};" \
425 "writenand_spl=nandrbl rbl;nand erase 0 3000;" \
426 "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
427 " 0 3000;nandrbl uboot\0" \
428 "writeuboot=nandrbl uboot;" \
429 "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
430 xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
431 ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
432 " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
433 xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
434 "update=run load writenand_spl writeuboot\0" \
435 "bootcmd=run net_nfs\0" \
436 "rootpath=/opt/eldk-arm/arm\0" \
437 "mtdids=" MTDIDS_DEFAULT "\0" \
438 "mtdparts=" MTDPARTS_DEFAULT "\0" \
440 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
441 "addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0" \
442 "addcon=setenv bootargs ${bootargs} console=ttyS0," \
444 "addip=setenv bootargs ${bootargs} " \
445 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
446 ":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0" \
447 "rootpath=/opt/eldk-arm/arm\0" \
448 "nfsargs=setenv bootargs root=/dev/nfs rw " \
449 "nfsroot=${serverip}:${rootpath}\0" \
450 "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
451 "kernel_addr_r=80600000\0" \
452 "load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \
453 "ubi_load_kernel=ubi part ubi 2048;ubifsmount ${img_volume};" \
454 "ubifsload ${kernel_addr_r} boot/uImage\0" \
455 "fit_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \
456 "img_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \
457 "img_file=" xstr(CONFIG_HOSTNAME) "/ait.itb\0" \
458 "header_addr=20000\0" \
459 "img_writeheader=nandrbl rbl;" \
460 "nand erase ${header_addr} ${pagesz};" \
461 "nand write ${img_addr_r} ${header_addr} ${pagesz};" \
463 "img_writespl=nandrbl rbl;nand erase 0 3000;" \
464 "nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \
465 "img_writeuboot=nandrbl uboot;" \
466 "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
467 xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
468 ";nand write ${img_addr_r} " \
469 xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
470 xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
471 "img_writedfenv=ubi part ubi 2048;" \
472 "ubi write ${img_addr_r} default ${filesize}\0" \
473 "img_volume=rootfs1\0" \
474 "img_writeramdisk=ubi part ubi 2048;" \
475 "ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \
476 "load_img=tftp ${fit_addr_r} ${img_file}\0" \
477 "net_nfs=run load_kernel; " \
478 "run nfsargs addip addcon addmtd addmisc;" \
479 "bootm ${kernel_addr_r}\0" \
480 "ubi_ubi=run ubi_load_kernel; " \
481 "run ubiargs addip addcon addmtd addmisc;" \
482 "bootm ${kernel_addr_r}\0" \
483 "ubiargs=setenv bootargs ubi.mtd=4,2048" \
484 " root=ubi0:${img_volume} rw rootfstype=ubifs\0" \
486 "dvn_app_vers=void\0" \
487 "dvn_boot_vers=void\0" \
488 "savenewvers=run savetmpparms restoreparms; saveenv;" \
489 "run restoretmpparms\0" \
490 "savetmpparms=setenv y_ipaddr ${ipaddr};" \
491 "setenv y_netmask ${netmask};" \
492 "setenv y_serverip ${serverip};" \
493 "setenv y_gatewayip ${gatewayip}\0" \
494 "saveparms=setenv x_ipaddr ${ipaddr};" \
495 "setenv x_netmask ${netmask};" \
496 "setenv x_serverip ${serverip};" \
497 "setenv x_gatewayip ${gatewayip}\0" \
498 "restoreparms=setenv ipaddr ${x_ipaddr};" \
499 "setenv netmask ${x_netmask};" \
500 "setenv serverip ${x_serverip};" \
501 "setenv gatewayip ${x_gatewayip}\0" \
502 "restoretmpparms=setenv ipaddr ${y_ipaddr};" \
503 "setenv netmask ${y_netmask};" \
504 "setenv serverip ${y_serverip};" \
505 "setenv gatewayip ${y_gatewayip}\0" \
508 /* USB Configuration */
509 #define CONFIG_USB_DAVINCI
510 #define CONFIG_MUSB_HCD
511 #define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
514 #define CONFIG_CMD_USB /* include support for usb cmd */
515 #define CONFIG_USB_STORAGE /* MSC class support */
516 #define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
517 #define CONFIG_CMD_FAT /* inclue support for FAT/storage */
518 #define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
520 #undef DAVINCI_DM365EVM
521 #define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
522 #define PINMUX4_USBDRVBUS_BITSET 0x2000
524 #endif /* __CONFIG_H */