3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 /************************************************************************
22 * canyonlands.h - configuration for Canyonlands (460EX)
23 ***********************************************************************/
27 /*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30 #define CONFIG_CANYONLANDS 1 /* Board is Canyonlands */
32 #define CONFIG_4xx 1 /* ... PPC4xx family */
33 #define CONFIG_460EX 1 /* Specific PPC460EX support */
35 #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
37 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
38 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
39 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
41 /*-----------------------------------------------------------------------
42 * Base addresses -- Note these are effective addresses where the
43 * actual resources get mapped (not physical addresses)
44 *----------------------------------------------------------------------*/
45 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
47 #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
48 #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
49 #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
51 #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
52 #define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
53 #define CFG_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
55 #define CFG_PCIE0_CFGBASE 0xc0000000
56 #define CFG_PCIE1_CFGBASE 0xc1000000
57 #define CFG_PCIE0_XCFGBASE 0xc3000000
58 #define CFG_PCIE1_XCFGBASE 0xc3001000
60 #define CFG_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
62 /* base address of inbound PCIe window */
63 #define CFG_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
66 #define CFG_NAND_ADDR 0xE0000000
67 #define CFG_BCSR_BASE 0xE1000000
68 #define CFG_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
69 #define CFG_FLASH_BASE 0xFC000000 /* later mapped to this addr */
70 #define CFG_FLASH_BASE_PHYS_H 0x4
71 #define CFG_FLASH_BASE_PHYS_L 0xCC000000
72 #define CFG_FLASH_BASE_PHYS (((u64)CFG_FLASH_BASE_PHYS_H << 32) | \
73 (u64)CFG_FLASH_BASE_PHYS_L)
74 #define CFG_FLASH_SIZE (64 << 20)
76 #define CFG_OCM_BASE 0xE3000000 /* OCM: 16k */
77 #define CFG_SRAM_BASE 0xE8000000 /* SRAM: 256k */
78 #define CFG_LOCAL_CONF_REGS 0xEF000000
80 #define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
82 #define CFG_MONITOR_BASE TEXT_BASE
83 #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
84 #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc()*/
86 /*-----------------------------------------------------------------------
87 * Initial RAM & stack pointer (placed in OCM)
88 *----------------------------------------------------------------------*/
89 #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
90 #define CFG_INIT_RAM_END (4 << 10)
91 #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
92 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
93 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
95 /*-----------------------------------------------------------------------
97 *----------------------------------------------------------------------*/
98 #define CONFIG_BAUDRATE 115200
99 #define CONFIG_SERIAL_MULTI 1
100 #undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
102 #define CFG_BAUDRATE_TABLE \
103 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
105 /*-----------------------------------------------------------------------
107 *----------------------------------------------------------------------*/
109 * Define here the location of the environment variables (FLASH).
111 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
112 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
113 #define CFG_NAND_CS 3 /* NAND chip connected to CSx */
115 #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
116 #define CFG_NAND_CS 0 /* NAND chip connected to CSx */
117 #define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
121 * IPL (Initial Program Loader, integrated inside CPU)
122 * Will load first 4k from NAND (SPL) into cache and execute it from there.
124 * SPL (Secondary Program Loader)
125 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
126 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
127 * controller and the NAND controller so that the special U-Boot image can be
128 * loaded from NAND to SDRAM.
131 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
132 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
134 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
135 * set up. While still running from cache, I experienced problems accessing
136 * the NAND controller. sr - 2006-08-25
138 #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
139 #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
140 #define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
141 #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
142 #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */
144 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
147 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
149 #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
150 #define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
153 * Now the NAND chip has to be defined (no autodetection used!)
155 #define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
156 #define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
157 #define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
158 #define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
159 #undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
161 #define CFG_NAND_ECCSIZE 256
162 #define CFG_NAND_ECCBYTES 3
163 #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
164 #define CFG_NAND_OOBSIZE 16
165 #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
166 #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
168 #ifdef CFG_ENV_IS_IN_NAND
170 * For NAND booting the environment is embedded in the U-Boot image. Please take
171 * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
173 #define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
174 #define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
175 #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
178 /*-----------------------------------------------------------------------
180 *----------------------------------------------------------------------*/
181 #define CFG_FLASH_CFI /* The flash is CFI compatible */
182 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
183 #define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
185 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
186 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
187 #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
189 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
190 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
192 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
193 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
195 #ifdef CFG_ENV_IS_IN_FLASH
196 #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
197 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
198 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
200 /* Address and size of Redundant Environment Sector */
201 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
202 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
203 #endif /* CFG_ENV_IS_IN_FLASH */
205 /*-----------------------------------------------------------------------
207 *----------------------------------------------------------------------*/
208 #define CFG_MAX_NAND_DEVICE 1
209 #define NAND_MAX_CHIPS 1
210 #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
211 #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
213 /*------------------------------------------------------------------------------
215 *----------------------------------------------------------------------------*/
216 #if !defined(CONFIG_NAND_U_BOOT)
218 * NAND booting U-Boot version uses a fixed initialization, since the whole
219 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
222 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
223 #define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
224 #define CONFIG_DDR_ECC 1 /* with ECC support */
225 #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
227 #define CFG_MBYTES_SDRAM 256 /* 256MB */
229 /*-----------------------------------------------------------------------
231 *----------------------------------------------------------------------*/
232 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
233 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
234 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
235 #define CFG_I2C_SLAVE 0x7F
237 #define CFG_I2C_MULTI_EEPROMS
238 #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
239 #define CFG_I2C_EEPROM_ADDR_LEN 1
240 #define CFG_EEPROM_PAGE_WRITE_ENABLE
241 #define CFG_EEPROM_PAGE_WRITE_BITS 3
242 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
244 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
245 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
246 #define CONFIG_DTT_AD7414 1 /* use AD7414 */
247 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
248 #define CFG_DTT_MAX_TEMP 70
249 #define CFG_DTT_LOW_TEMP -30
250 #define CFG_DTT_HYSTERESIS 3
252 /* RTC configuration */
253 #define CONFIG_RTC_M41T62 1
254 #define CFG_I2C_RTC_ADDR 0x68
256 /*-----------------------------------------------------------------------
258 *----------------------------------------------------------------------*/
259 #define CONFIG_IBM_EMAC4_V4 1
260 #define CONFIG_MII 1 /* MII PHY management */
261 #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
262 #define CONFIG_PHY1_ADDR 1
263 #define CONFIG_HAS_ETH0 1
264 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
265 #define CONFIG_NET_MULTI 1
267 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
268 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
269 #define CONFIG_PHY_DYNAMIC_ANEG 1
271 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
273 #define CONFIG_PREBOOT "echo;" \
274 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
277 #undef CONFIG_BOOTARGS
279 #define CONFIG_EXTRA_ENV_SETTINGS \
281 "hostname=canyonlands\0" \
282 "nfsargs=setenv bootargs root=/dev/nfs rw " \
283 "nfsroot=${serverip}:${rootpath}\0" \
284 "ramargs=setenv bootargs root=/dev/ram rw\0" \
285 "addip=setenv bootargs ${bootargs} " \
286 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
287 ":${hostname}:${netdev}:off panic=1\0" \
288 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
289 "net_nfs=tftp 200000 ${bootfile};" \
290 "run nfsargs addip addtty;" \
292 "net_nfs_fdt=tftp 200000 ${bootfile};" \
293 "tftp ${fdt_addr} ${fdt_file};" \
294 "run nfsargs addip addtty;" \
295 "bootm 200000 - ${fdt_addr}\0" \
296 "flash_nfs=run nfsargs addip addtty;" \
297 "bootm ${kernel_addr}\0" \
298 "flash_self=run ramargs addip addtty;" \
299 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
300 "rootpath=/opt/eldk/ppc_4xxFP\0" \
301 "bootfile=canyonlands/uImage\0" \
302 "fdt_file=canyonlands/canyonlands.dtb\0" \
303 "fdt_addr=400000\0" \
304 "kernel_addr=fc000000\0" \
305 "ramdisk_addr=fc200000\0" \
306 "initrd_high=30000000\0" \
307 "load=tftp 200000 canyonlands/u-boot.bin\0" \
308 "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
309 "cp.b ${fileaddr} fffa0000 ${filesize};" \
310 "setenv filesize;saveenv\0" \
311 "upd=run load update\0" \
312 "nload=tftp 200000 canyonlands/u-boot-nand.bin\0" \
313 "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
314 "setenv filesize;saveenv\0" \
315 "nupd=run nload nupdate\0" \
316 "pciconfighost=1\0" \
317 "pcie_mode=RP:RP\0" \
319 #define CONFIG_BOOTCOMMAND "run flash_self"
321 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
323 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
324 #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
329 #define CONFIG_BOOTP_BOOTFILESIZE
330 #define CONFIG_BOOTP_BOOTPATH
331 #define CONFIG_BOOTP_GATEWAY
332 #define CONFIG_BOOTP_HOSTNAME
333 #define CONFIG_BOOTP_SUBNETMASK
336 * Command line configuration.
338 #include <config_cmd_default.h>
340 #define CONFIG_CMD_ASKENV
341 #define CONFIG_CMD_DATE
342 #define CONFIG_CMD_DHCP
343 #define CONFIG_CMD_DTT
344 #define CONFIG_CMD_DIAG
345 #define CONFIG_CMD_EEPROM
346 #define CONFIG_CMD_ELF
347 #define CONFIG_CMD_FAT
348 #define CONFIG_CMD_I2C
349 #define CONFIG_CMD_IRQ
350 #define CONFIG_CMD_MII
351 #define CONFIG_CMD_NAND
352 #define CONFIG_CMD_NET
353 #define CONFIG_CMD_NFS
354 #define CONFIG_CMD_PCI
355 #define CONFIG_CMD_PING
356 #define CONFIG_CMD_REGINFO
357 #define CONFIG_CMD_SDRAM
359 /*-----------------------------------------------------------------------
360 * Miscellaneous configurable options
361 *----------------------------------------------------------------------*/
362 #define CFG_LONGHELP /* undef to save memory */
363 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
364 #if defined(CONFIG_CMD_KGDB)
365 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
367 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
369 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
370 #define CFG_MAXARGS 16 /* max number of command args */
371 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
373 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
374 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
376 #define CFG_LOAD_ADDR 0x100000 /* default load address */
377 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
379 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
381 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
382 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
383 #define CONFIG_LOOPW 1 /* enable loopw command */
384 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
385 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
386 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
387 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
389 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
390 #ifdef CFG_HUSH_PARSER
391 #define CFG_PROMPT_HUSH_PS2 "> "
394 /*-----------------------------------------------------------------------
396 *----------------------------------------------------------------------*/
398 #define CONFIG_PCI /* include pci support */
399 #define CONFIG_PCI_PNP /* do pci plug-and-play */
400 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
401 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
403 /* Board-specific PCI */
404 #define CFG_PCI_TARGET_INIT /* let board init pci target */
405 #undef CFG_PCI_MASTER_INIT
407 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
408 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
411 * For booting Linux, the board info and command line data
412 * have to be in the first 8 MB of memory, since this is
413 * the maximum mapped by the Linux kernel during initialization.
415 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
418 * Internal Definitions
420 #if defined(CONFIG_CMD_KGDB)
421 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
422 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
425 /*-----------------------------------------------------------------------
426 * External Bus Controller (EBC) Setup
427 *----------------------------------------------------------------------*/
430 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
431 * boot EBC mapping only supports a maximum of 16MBytes
432 * (4.ff00.0000 - 4.ffff.ffff).
433 * To solve this problem, the FLASH has to get remapped to another
434 * EBC address which accepts bigger regions:
436 * 0xfc00.0000 -> 4.cc00.0000
439 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
440 /* Memory Bank 3 (NOR-FLASH) initialization */
441 #define CFG_EBC_PB3AP 0x10055e00
442 #define CFG_EBC_PB3CR (CFG_BOOT_BASE_ADDR | 0x9a000)
444 /* Memory Bank 0 (NAND-FLASH) initialization */
445 #define CFG_EBC_PB0AP 0x018003c0
446 #define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
448 /* Memory Bank 0 (NOR-FLASH) initialization */
449 #define CFG_EBC_PB0AP 0x10055e00
450 #define CFG_EBC_PB0CR (CFG_BOOT_BASE_ADDR | 0x9a000)
452 /* Memory Bank 3 (NAND-FLASH) initialization */
453 #define CFG_EBC_PB3AP 0x018003c0
454 #define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
457 /* Memory Bank 2 (CPLD) initialization */
458 #define CFG_EBC_PB2AP 0x00804240
459 #define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
461 #define CFG_EBC_CFG 0xB8400000 /* EBC0_CFG */
464 * PPC4xx GPIO Configuration
466 #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
469 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
470 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
471 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
472 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
473 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
474 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
475 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
476 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
477 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
478 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
479 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
480 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
481 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
482 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
483 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
484 {GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
485 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
486 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
487 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
488 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
489 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
490 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
491 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
492 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
493 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
494 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
495 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
496 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
497 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
498 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
499 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
500 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
504 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
505 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
506 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
507 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
508 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
509 {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
510 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
511 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
512 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
513 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
514 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
515 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
516 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
517 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
518 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
519 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
520 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
521 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
522 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
523 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
524 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
525 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
526 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
527 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
528 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
529 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
530 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
531 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
532 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
533 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
534 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
535 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
539 /* pass open firmware flat tree */
540 #define CONFIG_OF_LIBFDT 1
541 #define CONFIG_OF_BOARD_SETUP 1
543 #endif /* __CONFIG_H */