2 * Copyright (c) 2011 The Chromium OS Authors.
4 * Graeme Russ, graeme.russ@gmail.com.
6 * SPDX-License-Identifier: GPL-2.0+
10 * board/config.h - configuration options, board specific
16 #include <configs/x86-common.h>
19 #define CONFIG_SYS_MONITOR_LEN (1 << 20)
21 #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000
22 #define CONFIG_BOARD_EARLY_INIT_F
24 #define CONFIG_NR_DRAM_BANKS 8
25 #define CONFIG_X86_MRC_ADDR 0xfffa0000
26 #define CONFIG_CACHE_MRC_SIZE_KB 512
28 #define CONFIG_X86_SERIAL
30 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
31 PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
32 {PCI_VENDOR_ID_INTEL, \
33 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
34 {PCI_VENDOR_ID_INTEL, \
35 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
36 {PCI_VENDOR_ID_INTEL, \
37 PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
39 #define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin
40 #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
42 #define CONFIG_PCI_MEM_BUS 0xe0000000
43 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
44 #define CONFIG_PCI_MEM_SIZE 0x10000000
46 #define CONFIG_PCI_PREF_BUS 0xd0000000
47 #define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
48 #define CONFIG_PCI_PREF_SIZE 0x10000000
50 #define CONFIG_PCI_IO_BUS 0x1000
51 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
52 #define CONFIG_PCI_IO_SIZE 0xefff
54 #define CONFIG_SYS_EARLY_PCI_INIT
55 #define CONFIG_PCI_PNP
57 #define CONFIG_BIOSEMU
58 #define VIDEO_IO_OFFSET 0
59 #define CONFIG_X86EMU_RAW_IO
61 #define CONFIG_CROS_EC
62 #define CONFIG_CROS_EC_LPC
63 #define CONFIG_CMD_CROS_EC
64 #define CONFIG_ARCH_EARLY_INIT_R
66 #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
67 "stdout=vga,serial\0" \
70 #endif /* __CONFIG_H */