2 * (C) Copyright 2003-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 * High Level Configuration Options
14 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
15 #define CONFIG_CM5200 1 /* ... on CM5200 platform */
17 #define CONFIG_SYS_TEXT_BASE 0xfc000000
19 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
24 #define CONFIG_CMD_BSP
25 #define CONFIG_CMD_DATE
26 #define CONFIG_CMD_DIAG
27 #define CONFIG_CMD_JFFS2
28 #define CONFIG_CMD_REGINFO
31 * Serial console configuration
33 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
34 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
37 * Ethernet configuration
39 #define CONFIG_MPC5xxx_FEC 1
40 #define CONFIG_MPC5xxx_FEC_MII100
41 #define CONFIG_PHY_ADDR 0x00
42 #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
43 /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
44 #define CONFIG_MISC_INIT_R 1
45 #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
50 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
51 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
52 /* List of I2C addresses to be verified by POST */
53 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
55 CONFIG_SYS_I2C_EEPROM}
57 /* display image timestamps */
58 #define CONFIG_TIMESTAMP 1
63 #define CONFIG_PREBOOT "echo;" \
64 "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
66 #undef CONFIG_BOOTARGS
69 * Default environment settings
71 #define CONFIG_EXTRA_ENV_SETTINGS \
73 "netmask=255.255.0.0\0" \
74 "ipaddr=192.168.160.33\0" \
75 "serverip=192.168.1.1\0" \
76 "gatewayip=192.168.1.1\0" \
78 "u-boot_addr=100000\0" \
79 "kernel_addr=200000\0" \
80 "kernel_addr_flash=fc0c0000\0" \
82 "fdt_addr_flash=fc0a0000\0" \
83 "ramdisk_addr=500000\0" \
84 "rootpath=/opt/eldk-4.1/ppc_6xx\0" \
85 "u-boot=/tftpboot/cm5200/u-boot.bin\0" \
86 "bootfile_fdt=/tftpboot/cm5200/uImage\0" \
87 "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
88 "load=tftp ${u-boot_addr} ${u-boot}\0" \
89 "update=prot off fc000000 +${filesize}; " \
90 "era fc000000 +${filesize}; " \
91 "cp.b ${u-boot_addr} fc000000 ${filesize}; " \
92 "prot on fc000000 +${filesize}\0" \
93 "nfsargs=setenv bootargs root=/dev/nfs rw " \
94 "nfsroot=${serverip}:${rootpath}\0" \
95 "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
96 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
97 "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
98 "addcons=setenv bootargs ${bootargs} " \
99 "console=${console},${baudrate}\0" \
100 "addip=setenv bootargs ${bootargs} " \
101 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
102 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
103 "flash_flash=run flashargs addinit addip addcons;" \
104 "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
105 "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
106 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
107 "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
109 #define CONFIG_BOOTCOMMAND "run flash_flash"
112 * Low level configuration
116 * Clock configuration
118 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
119 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
124 #define CONFIG_SYS_MBAR 0xF0000000
125 #define CONFIG_SYS_SDRAM_BASE 0x00000000
126 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
128 #define CONFIG_SYS_LOWBOOT 1
130 /* Use ON-Chip SRAM until RAM will be available */
131 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
133 /* preserve space for the post_word at end of on-chip SRAM */
134 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
136 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
139 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
140 #define CONFIG_BOARD_TYPES 1 /* we use board_type */
142 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
145 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
146 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
147 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
150 * Flash configuration
152 #define CONFIG_SYS_FLASH_CFI 1
153 #define CONFIG_FLASH_CFI_DRIVER 1
154 #define CONFIG_SYS_FLASH_BASE 0xfc000000
155 /* we need these despite using CFI */
156 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
157 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
158 #define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
160 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
161 #define CONFIG_SYS_RAMBOOT 1
162 #undef CONFIG_SYS_LOWBOOT
166 * Chip selects configuration
168 /* Boot Chipselect */
169 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
170 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
171 #define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
172 /* use board_early_init_r to enable flash write in CS_BOOT */
173 #define CONFIG_BOARD_EARLY_INIT_R
175 /* Flash memory addressing */
176 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
177 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
179 /* No burst, dead cycle = 1 for CS0 (Flash) */
180 #define CONFIG_SYS_CS_BURST 0x00000000
181 #define CONFIG_SYS_CS_DEADCYCLE 0x00000001
184 * SDRAM configuration
185 * settings for k4s561632E-xx75, assuming XLB = 132 MHz
187 #define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
188 #define SDRAM_CONTROL 0x514F0000
189 #define SDRAM_CONFIG1 0xE2333900
190 #define SDRAM_CONFIG2 0x8EE70000
195 #define CONFIG_CMD_MTDPARTS 1
196 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
197 #define CONFIG_FLASH_CFI_MTD
198 #define MTDIDS_DEFAULT "nor0=cm5200-0"
199 #define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
200 "384k(uboot),128k(env)," \
201 "128k(redund_env),128k(dtb)," \
202 "2m(kernel),27904k(rootfs)," \
208 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
209 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
210 #define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */
211 #define CONFIG_SYS_I2C_SLAVE 0x0
212 #define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
213 #define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */
218 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
223 #define CONFIG_USB_OHCI 1
224 #define CONFIG_USB_CLOCK 0x0001BBBB
225 #define CONFIG_USB_CONFIG 0x00001000
226 /* Partitions (for USB) */
229 * Invoke our last_stage_init function - needed by fwupdate
231 #define CONFIG_LAST_STAGE_INIT 1
234 * Environment settings
236 #define CONFIG_ENV_IS_IN_FLASH 1
237 #define CONFIG_ENV_SIZE 0x10000
238 #define CONFIG_ENV_SECT_SIZE 0x20000
239 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
240 /* Configuration of redundant environment */
241 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
242 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
245 * Pin multiplexing configuration
249 * CS1/GPIO_WKUP_6: GPIO (default)
250 * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
252 * Ether: Ethernet 100Mbit with MD
253 * PCI_DIS: PCI controller disabled
255 * PSC3: SPI with UART3
259 #define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44
262 * Miscellaneous configurable options
264 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
265 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
266 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
267 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
268 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
270 #define CONFIG_SYS_ALT_MEMTEST 1
271 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
272 #define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
274 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
277 * Various low-level settings
279 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
280 #define CONFIG_SYS_HID0_FINAL HID0_ICE
282 #define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */
285 * Cache Configuration
287 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
288 #ifdef CONFIG_CMD_KGDB
289 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
293 * Flat Device Tree support
295 #define OF_CPU "PowerPC,5200@0"
296 #define OF_SOC "soc5200@f0000000"
297 #define OF_TBCLK (bd->bi_busfreq / 4)
298 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
300 #endif /* __CONFIG_H */