2 * (C) Copyright 2003-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_DISPLAY_BOARDINFO
16 * High Level Configuration Options
18 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
19 #define CONFIG_CM5200 1 /* ... on CM5200 platform */
21 #define CONFIG_SYS_TEXT_BASE 0xfc000000
23 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
28 #define CONFIG_CMD_ASKENV
29 #define CONFIG_CMD_BSP
30 #define CONFIG_CMD_DATE
31 #define CONFIG_CMD_DIAG
32 #define CONFIG_CMD_FAT
33 #define CONFIG_CMD_JFFS2
34 #define CONFIG_CMD_MII
35 #define CONFIG_CMD_REGINFO
38 * Serial console configuration
40 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
41 #define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */
42 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
43 #define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
46 * Ethernet configuration
48 #define CONFIG_MPC5xxx_FEC 1
49 #define CONFIG_MPC5xxx_FEC_MII100
50 #define CONFIG_PHY_ADDR 0x00
51 #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
52 /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
53 #define CONFIG_MISC_INIT_R 1
54 #define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
59 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
60 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
61 /* List of I2C addresses to be verified by POST */
62 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
64 CONFIG_SYS_I2C_EEPROM}
66 /* display image timestamps */
67 #define CONFIG_TIMESTAMP 1
72 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
73 #define CONFIG_PREBOOT "echo;" \
74 "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
76 #undef CONFIG_BOOTARGS
79 * Default environment settings
81 #define CONFIG_EXTRA_ENV_SETTINGS \
83 "netmask=255.255.0.0\0" \
84 "ipaddr=192.168.160.33\0" \
85 "serverip=192.168.1.1\0" \
86 "gatewayip=192.168.1.1\0" \
88 "u-boot_addr=100000\0" \
89 "kernel_addr=200000\0" \
90 "kernel_addr_flash=fc0c0000\0" \
92 "fdt_addr_flash=fc0a0000\0" \
93 "ramdisk_addr=500000\0" \
94 "rootpath=/opt/eldk-4.1/ppc_6xx\0" \
95 "u-boot=/tftpboot/cm5200/u-boot.bin\0" \
96 "bootfile_fdt=/tftpboot/cm5200/uImage\0" \
97 "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
98 "load=tftp ${u-boot_addr} ${u-boot}\0" \
99 "update=prot off fc000000 +${filesize}; " \
100 "era fc000000 +${filesize}; " \
101 "cp.b ${u-boot_addr} fc000000 ${filesize}; " \
102 "prot on fc000000 +${filesize}\0" \
103 "nfsargs=setenv bootargs root=/dev/nfs rw " \
104 "nfsroot=${serverip}:${rootpath}\0" \
105 "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
106 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
107 "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
108 "addcons=setenv bootargs ${bootargs} " \
109 "console=${console},${baudrate}\0" \
110 "addip=setenv bootargs ${bootargs} " \
111 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
112 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
113 "flash_flash=run flashargs addinit addip addcons;" \
114 "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
115 "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
116 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
117 "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
119 #define CONFIG_BOOTCOMMAND "run flash_flash"
122 * Low level configuration
126 * Clock configuration
128 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
129 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
134 #define CONFIG_SYS_MBAR 0xF0000000
135 #define CONFIG_SYS_SDRAM_BASE 0x00000000
136 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
138 #define CONFIG_SYS_LOWBOOT 1
140 /* Use ON-Chip SRAM until RAM will be available */
141 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
143 /* preserve space for the post_word at end of on-chip SRAM */
144 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
146 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
149 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
150 #define CONFIG_BOARD_TYPES 1 /* we use board_type */
152 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
154 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
155 #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
156 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
157 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
160 * Flash configuration
162 #define CONFIG_SYS_FLASH_CFI 1
163 #define CONFIG_FLASH_CFI_DRIVER 1
164 #define CONFIG_SYS_FLASH_BASE 0xfc000000
165 /* we need these despite using CFI */
166 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
167 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
168 #define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
171 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
172 #define CONFIG_SYS_RAMBOOT 1
173 #undef CONFIG_SYS_LOWBOOT
178 * Chip selects configuration
180 /* Boot Chipselect */
181 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
182 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
183 #define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
184 /* use board_early_init_r to enable flash write in CS_BOOT */
185 #define CONFIG_BOARD_EARLY_INIT_R
187 /* Flash memory addressing */
188 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
189 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
191 /* No burst, dead cycle = 1 for CS0 (Flash) */
192 #define CONFIG_SYS_CS_BURST 0x00000000
193 #define CONFIG_SYS_CS_DEADCYCLE 0x00000001
196 * SDRAM configuration
197 * settings for k4s561632E-xx75, assuming XLB = 132 MHz
199 #define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
200 #define SDRAM_CONTROL 0x514F0000
201 #define SDRAM_CONFIG1 0xE2333900
202 #define SDRAM_CONFIG2 0x8EE70000
207 #define CONFIG_CMD_MTDPARTS 1
208 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
209 #define CONFIG_FLASH_CFI_MTD
210 #define MTDIDS_DEFAULT "nor0=cm5200-0"
211 #define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
212 "384k(uboot),128k(env)," \
213 "128k(redund_env),128k(dtb)," \
214 "2m(kernel),27904k(rootfs)," \
220 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
221 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
222 #define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */
223 #define CONFIG_SYS_I2C_SLAVE 0x0
224 #define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
225 #define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */
230 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
235 #define CONFIG_USB_OHCI 1
236 #define CONFIG_USB_STORAGE 1
237 #define CONFIG_USB_CLOCK 0x0001BBBB
238 #define CONFIG_USB_CONFIG 0x00001000
239 /* Partitions (for USB) */
240 #define CONFIG_MAC_PARTITION 1
241 #define CONFIG_DOS_PARTITION 1
242 #define CONFIG_ISO_PARTITION 1
245 * Invoke our last_stage_init function - needed by fwupdate
247 #define CONFIG_LAST_STAGE_INIT 1
250 * Environment settings
252 #define CONFIG_ENV_IS_IN_FLASH 1
253 #define CONFIG_ENV_SIZE 0x10000
254 #define CONFIG_ENV_SECT_SIZE 0x20000
255 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
256 /* Configuration of redundant environment */
257 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
258 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
261 * Pin multiplexing configuration
265 * CS1/GPIO_WKUP_6: GPIO (default)
266 * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
268 * Ether: Ethernet 100Mbit with MD
269 * PCI_DIS: PCI controller disabled
271 * PSC3: SPI with UART3
275 #define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44
278 * Miscellaneous configurable options
280 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
281 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
282 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
283 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
284 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
286 #define CONFIG_SYS_ALT_MEMTEST 1
287 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
288 #define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
290 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
293 * Various low-level settings
295 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
296 #define CONFIG_SYS_HID0_FINAL HID0_ICE
298 #define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */
301 * Cache Configuration
303 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
304 #ifdef CONFIG_CMD_KGDB
305 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
309 * Flat Device Tree support
311 #define OF_CPU "PowerPC,5200@0"
312 #define OF_SOC "soc5200@f0000000"
313 #define OF_TBCLK (bd->bi_busfreq / 4)
314 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
316 #endif /* __CONFIG_H */