2 * Config file for Compulab CM-T335 board
4 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
6 * Author: Ilya Ledvich <ilya@compulab.co.il>
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef __CONFIG_CM_T335_H
12 #define __CONFIG_CM_T335_H
14 #define CONFIG_CM_T335
16 #include <configs/ti_am335x_common.h>
19 #undef CONFIG_OMAP3_SPI
20 #undef CONFIG_BOOTCOUNT_LIMIT
21 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
23 #undef CONFIG_MAX_RAM_BANK_SIZE
24 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
26 #define CONFIG_MACH_TYPE MACH_TYPE_CM_T335
29 #define V_OSCK 25000000 /* Clock output from T2 */
30 #define V_SCLK (V_OSCK)
32 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
34 #ifndef CONFIG_SPL_BUILD
37 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
38 "mmcrootfstype=ext4\0" \
39 "mmcargs=setenv bootargs console=${console} " \
41 "rootfstype=${mmcrootfstype}\0" \
42 "mmcboot=echo Booting from mmc ...; " \
47 "mtdids=" MTDIDS_DEFAULT "\0" \
48 "mtdparts=" MTDPARTS_DEFAULT "\0" \
49 "nandroot=ubi0:rootfs rw\0" \
50 "nandrootfstype=ubifs\0" \
51 "nandargs=setenv bootargs console=${console} " \
53 "rootfstype=${nandrootfstype} " \
54 "ubi.mtd=${rootfs_name}\0" \
55 "nandboot=echo Booting from nand ...; " \
57 "nboot ${loadaddr} nand0 900000; " \
60 #define CONFIG_EXTRA_ENV_SETTINGS \
61 "loadaddr=82000000\0" \
62 "console=ttyO0,115200n8\0" \
63 "rootfs_name=rootfs\0" \
64 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
65 "bootscript=echo Running bootscript from mmc ...; " \
66 "source ${loadaddr}\0" \
67 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
71 #define CONFIG_BOOTCOMMAND \
72 "mmc dev ${mmcdev}; if mmc rescan; then " \
73 "if run loadbootscript; then " \
76 "if run loaduimage; then " \
78 "else run nandboot; " \
81 "else run nandboot; fi"
82 #endif /* CONFIG_SPL_BUILD */
84 #define CONFIG_TIMESTAMP
85 #define CONFIG_SYS_AUTOLOAD "no"
87 /* Serial console configuration */
88 #define CONFIG_CONS_INDEX 1
89 #define CONFIG_SERIAL1 1 /* UART0 */
91 /* NS16550 Configuration */
92 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
93 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
95 /* I2C Configuration */
96 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
97 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
98 #define CONFIG_SYS_I2C_EEPROM_BUS 0
103 #define CONFIG_PHY_ATHEROS
106 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
107 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
108 CONFIG_SYS_NAND_PAGE_SIZE)
109 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
110 #define CONFIG_SYS_NAND_OOBSIZE 64
111 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
112 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
113 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
114 10, 11, 12, 13, 14, 15, 16, 17, \
115 18, 19, 20, 21, 22, 23, 24, 25, \
116 26, 27, 28, 29, 30, 31, 32, 33, \
117 34, 35, 36, 37, 38, 39, 40, 41, \
118 42, 43, 44, 45, 46, 47, 48, 49, \
119 50, 51, 52, 53, 54, 55, 56, 57, }
121 #define CONFIG_SYS_NAND_ECCSIZE 512
122 #define CONFIG_SYS_NAND_ECCBYTES 14
124 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
126 #undef CONFIG_SYS_NAND_U_BOOT_OFFS
127 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
129 #define MTDIDS_DEFAULT "nand0=nand"
130 #define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \
131 "1m(u-boot),1m(u-boot-env)," \
132 "1m(dtb),4m(splash)," \
133 "6m(kernel),-(rootfs)"
134 #define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
135 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
136 #define CONFIG_SYS_NAND_ONFI_DETECTION
137 #ifdef CONFIG_SPL_OS_BOOT
138 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000
141 /* GPIO pin + bank to pin ID mapping */
142 #define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
145 /* Status LED polarity is inversed, so init it in the "off" state */
148 #define CONFIG_ENV_EEPROM_IS_ON_I2C
149 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
150 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
151 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
152 #define CONFIG_SYS_EEPROM_SIZE 256
154 #ifndef CONFIG_SPL_BUILD
156 * Enable PCA9555 at I2C0-0x26.
157 * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
159 #define CONFIG_PCA953X
160 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x26
161 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} }
162 #endif /* CONFIG_SPL_BUILD */
164 #endif /* __CONFIG_CM_T335_H */