2 * (C) Copyright 2011 CompuLab, Ltd.
3 * Mike Rapoport <mike@compulab.co.il>
4 * Igor Grinberg <grinberg@compulab.co.il>
6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
12 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
14 * SPDX-License-Identifier: GPL-2.0+
20 #define CONFIG_SYS_CACHELINE_SIZE 64
23 * High Level Configuration Options
25 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
27 #define CONFIG_SDRC /* The chip has SDRC controller */
29 #include <asm/arch/cpu.h> /* get chip and board defs */
30 #include <asm/arch/omap.h>
33 #define V_OSCK 26000000 /* Clock output from T2 */
34 #define V_SCLK (V_OSCK >> 1)
36 #define CONFIG_MISC_INIT_R
38 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
39 #define CONFIG_SETUP_MEMORY_TAGS
40 #define CONFIG_INITRD_TAG
41 #define CONFIG_REVISION_TAG
42 #define CONFIG_SERIAL_TAG
45 * Size of malloc() pool
47 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
56 * NS16550 Configuration
58 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
60 #define CONFIG_SYS_NS16550_SERIAL
61 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
62 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
65 * select serial console configuration
67 #define CONFIG_CONS_INDEX 3
68 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
69 #define CONFIG_SERIAL3 3 /* UART3 */
71 /* allow to overwrite serial and ethaddr */
72 #define CONFIG_ENV_OVERWRITE
73 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
77 #define CONFIG_USB_OMAP3
78 #define CONFIG_USB_MUSB_UDC
79 #define CONFIG_TWL4030_USB
81 /* USB device configuration */
82 #define CONFIG_USB_DEVICE
83 #define CONFIG_USB_TTY
85 /* commands to include */
86 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
87 #define CONFIG_MTD_PARTITIONS
88 #define MTDIDS_DEFAULT "nand0=nand"
89 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
90 "1920k(u-boot),256k(u-boot-env),"\
93 #define CONFIG_CMD_NAND /* NAND support */
95 #define CONFIG_SYS_I2C
96 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
97 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
98 #define CONFIG_SYS_I2C_OMAP34XX
99 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
100 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
101 #define CONFIG_SYS_I2C_EEPROM_BUS 0
102 #define CONFIG_I2C_MULTI_BUS
107 #define CONFIG_TWL4030_LED
112 #define CONFIG_NAND_OMAP_GPMC
113 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
115 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
116 /* to access nand at */
118 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
121 /* Environment information */
122 #define CONFIG_EXTRA_ENV_SETTINGS \
123 "loadaddr=0x82000000\0" \
125 "console=ttyO2,115200n8\0" \
128 "dvimode=1024x768MR-16@60\0" \
129 "defaultdisplay=dvi\0" \
131 "mmcroot=/dev/mmcblk0p2 rw\0" \
132 "mmcrootfstype=ext4 rootwait\0" \
133 "nandroot=/dev/mtdblock4 rw\0" \
134 "nandrootfstype=ubifs\0" \
135 "mmcargs=setenv bootargs console=${console} " \
136 "mpurate=${mpurate} " \
138 "omapfb.mode=dvi:${dvimode} " \
139 "omapdss.def_disp=${defaultdisplay} " \
141 "rootfstype=${mmcrootfstype}\0" \
142 "nandargs=setenv bootargs console=${console} " \
143 "mpurate=${mpurate} " \
145 "omapfb.mode=dvi:${dvimode} " \
146 "omapdss.def_disp=${defaultdisplay} " \
147 "root=${nandroot} " \
148 "rootfstype=${nandrootfstype}\0" \
149 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
150 "bootscript=echo Running bootscript from mmc ...; " \
151 "source ${loadaddr}\0" \
152 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
153 "mmcboot=echo Booting from mmc ...; " \
155 "bootm ${loadaddr}\0" \
156 "nandboot=echo Booting from nand ...; " \
158 "nand read ${loadaddr} 2a0000 400000; " \
159 "bootm ${loadaddr}\0" \
161 #define CONFIG_BOOTCOMMAND \
162 "mmc dev ${mmcdev}; if mmc rescan; then " \
163 "if run loadbootscript; then " \
166 "if run loaduimage; then " \
168 "else run nandboot; " \
171 "else run nandboot; fi"
174 * Miscellaneous configurable options
176 #define CONFIG_AUTO_COMPLETE
177 #define CONFIG_CMDLINE_EDITING
178 #define CONFIG_TIMESTAMP
179 #define CONFIG_SYS_AUTOLOAD "no"
180 #define CONFIG_SYS_LONGHELP /* undef to save memory */
181 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
182 /* Print Buffer Size */
183 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
184 sizeof(CONFIG_SYS_PROMPT) + 16)
185 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
186 /* Boot Argument Buffer Size */
187 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
189 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
191 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
192 0x01F00000) /* 31MB */
194 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
198 * OMAP3 has 12 GP timers, they can be driven by the system clock
199 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
200 * This rate is divided by a local divisor.
202 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
203 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
205 /*-----------------------------------------------------------------------
206 * Physical Memory Map
208 #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
209 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
211 /*-----------------------------------------------------------------------
212 * FLASH and environment organization
215 /* **** PISMO SUPPORT *** */
216 /* Monitor at start of flash */
217 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
218 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
220 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
221 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
222 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
224 #if defined(CONFIG_CMD_NET)
225 #define CONFIG_SMC911X
226 #define CONFIG_SMC911X_32_BIT
227 #define CM_T3X_SMC911X_BASE 0x2C000000
228 #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
229 #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
230 #endif /* (CONFIG_CMD_NET) */
232 /* additions for new relocation code, must be added to all boards */
233 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
234 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
235 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
236 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
237 CONFIG_SYS_INIT_RAM_SIZE - \
238 GENERATED_GBL_DATA_SIZE)
241 #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
243 #define CONFIG_SPLASHIMAGE_GUARD
245 /* Display Configuration */
246 #define CONFIG_VIDEO_OMAP3
247 #define LCD_BPP LCD_COLOR16
249 #define CONFIG_SPLASH_SCREEN
250 #define CONFIG_SPLASH_SOURCE
251 #define CONFIG_BMP_16BPP
252 #define CONFIG_SCF0403_LCD
254 #define CONFIG_OMAP3_SPI
256 /* Defines for SPL */
257 #define CONFIG_SPL_FRAMEWORK
258 #define CONFIG_SPL_NAND_SIMPLE
260 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
261 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
263 #define CONFIG_SPL_NAND_BASE
264 #define CONFIG_SPL_NAND_DRIVERS
265 #define CONFIG_SPL_NAND_ECC
266 #define CONFIG_SPL_OMAP3_ID_NAND
267 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
269 /* NAND boot config */
270 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
271 #define CONFIG_SYS_NAND_PAGE_COUNT 64
272 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
273 #define CONFIG_SYS_NAND_OOBSIZE 64
274 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
275 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
277 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
278 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
280 #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
282 #define CONFIG_SYS_NAND_ECCSIZE 512
283 #define CONFIG_SYS_NAND_ECCBYTES 3
284 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
286 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
287 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
289 #define CONFIG_SPL_TEXT_BASE 0x40200800
290 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
291 CONFIG_SPL_TEXT_BASE)
294 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
295 * older x-loader implementations. And move the BSS area so that it
296 * doesn't overlap with TEXT_BASE.
298 #define CONFIG_SYS_TEXT_BASE 0x80008000
299 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
300 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
302 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
303 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
306 #define CONFIG_ENV_EEPROM_IS_ON_I2C
307 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
308 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
309 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
310 #define CONFIG_SYS_EEPROM_SIZE 256
312 #endif /* __CONFIG_H */