2 * 2004-2005 Gary Jennejohn <garyj@denx.de>
4 * Configuration settings for the CMC PU2 board.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* ARM asynchronous clock */
29 #define AT91C_MAIN_CLOCK 207360000 /* from 18.432 MHz crystal (18432000 / 4 * 45) */
30 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK/3) /* peripheral clock */
32 #define AT91_SLOW_CLOCK 32768 /* slow clock */
34 #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
35 #define CONFIG_CMC_PU2 1 /* on an CMC_PU2 Board */
36 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
37 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
38 #define CONFIG_SETUP_MEMORY_TAGS 1
39 #define CONFIG_INITRD_TAG 1
41 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
42 #define CFG_USE_MAIN_OSCILLATOR 1
44 #define MC_PUIA_VAL 0x00000000
45 #define MC_PUP_VAL 0x00000000
46 #define MC_PUER_VAL 0x00000000
47 #define MC_ASR_VAL 0x00000000
48 #define MC_AASR_VAL 0x00000000
49 #define EBI_CFGR_VAL 0x00000000
50 #define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
53 #define PLLAR_VAL 0x202CBE04 /* 207.360 MHz for PCK */
54 #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
55 #define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
58 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
59 #define PIOC_BSR_VAL 0x00000000
60 #define PIOC_PDR_VAL 0xFFFF0000
61 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
62 #define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */
63 #define SDRAM 0x20000000 /* address of the SDRAM */
64 #define SDRAM1 0x20000080 /* address of the SDRAM */
65 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */
66 #define SDRC_MR_VAL 0x00000002 /* Precharge All */
67 #define SDRC_MR_VAL1 0x00000004 /* refresh */
68 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
69 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
70 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
71 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
74 * Size of malloc() pool
76 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
77 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
79 #define CONFIG_BAUDRATE 9600
81 #define CFG_AT91C_BRGR_DIVISOR 450 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK /(baudrate * 16) */
87 /* define one of these to choose the DBGU, USART0 or USART1 as console */
92 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
94 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
96 #define CONFIG_HARD_I2C
98 #ifdef CONFIG_HARD_I2C
99 #define CFG_I2C_SPEED 0 /* not used */
100 #define CFG_I2C_SLAVE 0 /* not used */
101 #define CONFIG_RTC_RS5C372A /* RICOH I2C RTC */
102 #define CFG_I2C_RTC_ADDR 0x32
103 #define CFG_I2C_EEPROM_ADDR 0x50
104 #define CFG_I2C_EEPROM_ADDR_LEN 1
105 #define CFG_I2C_EEPROM_ADDR_OVERFLOW
107 /* still about 20 kB free with this defined */
110 #define CONFIG_BOOTDELAY 3
112 #ifdef CONFIG_HARD_I2C
113 #define CONFIG_COMMANDS \
121 ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
123 #define CONFIG_COMMANDS \
128 ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
129 #define CONFIG_TIMESTAMP
133 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
134 #include <cmd_confdefs.h>
136 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
137 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
139 #define CONFIG_NR_DRAM_BANKS 1
140 #define PHYS_SDRAM 0x20000000
141 #define PHYS_SDRAM_SIZE 0x1000000 /* 16 megs */
143 #define CFG_MEMTEST_START PHYS_SDRAM
144 #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
146 #define CONFIG_DRIVER_ETHER
147 #define CONFIG_NET_RETRY_COUNT 20
148 #define CONFIG_AT91C_USE_RMII
150 #define CONFIG_HAS_DATAFLASH 1
151 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
152 #define CFG_MAX_DATAFLASH_BANKS 2
153 #define CFG_MAX_DATAFLASH_PAGES 16384
154 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
155 #define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
157 #define PHYS_FLASH_1 0x10000000
158 #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
159 #define CFG_FLASH_BASE PHYS_FLASH_1
160 #define CFG_MONITOR_BASE CFG_FLASH_BASE
161 #define CFG_MAX_FLASH_BANKS 1
162 #define CFG_MAX_FLASH_SECT 256
163 #define CFG_FLASH_ERASE_TOUT (11 * CFG_HZ) /* Timeout for Flash Erase */
164 #define CFG_FLASH_WRITE_TOUT ( 2 * CFG_HZ) /* Timeout for Flash Write */
166 #define CFG_ENV_IS_IN_FLASH 1
167 #define CFG_ENV_OFFSET 0x20000 /* after u-boot.bin */
168 #define CFG_ENV_SECT_SIZE (64 << 10) /* sectors are 64 kB */
169 #define CFG_ENV_SIZE (16 << 10) /* Use only 16 kB */
171 #define CFG_LOAD_ADDR 0x21000000 /* default load address */
173 #define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
175 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
176 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
177 #define CFG_MAXARGS 32 /* max number of command args */
178 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
181 /*-----------------------------------------------------------------------
182 * Board specific extension for bd_info
184 * This structure is embedded in the global bd_info (bd_t) structure
185 * and can be used by the board specific code (eg board/...)
189 /* helper variable for board environment handling
191 * env_crc_valid == 0 => uninitialised
192 * env_crc_valid > 0 => environment crc in flash is valid
193 * env_crc_valid < 0 => environment crc in flash is invalid
197 #endif /* __ASSEMBLY__ */
200 #define CFG_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */
201 /* AT91C_TC_TIMER_DIV1_CLOCK */
203 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
205 #ifdef CONFIG_USE_IRQ
206 #error CONFIG_USE_IRQ not supported
209 #endif /* __CONFIG_H */