3 * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
26 * Discription: Config header file for cmi
27 * board using an MPC5xx CPU
35 * High Level Configuration Options
38 #define CONFIG_MPC555 1 /* This is an MPC555 CPU */
39 #define CONFIG_CMI 1 /* Using the customized cmi board */
41 /* Serial Console Configuration */
42 #define CONFIG_5xx_CONS_SCI1
43 #undef CONFIG_5xx_CONS_SCI2
45 #define CONFIG_BAUDRATE 57600
51 #define CONFIG_BOOTP_BOOTFILESIZE
52 #define CONFIG_BOOTP_BOOTPATH
53 #define CONFIG_BOOTP_GATEWAY
54 #define CONFIG_BOOTP_HOSTNAME
58 * Command line configuration.
60 #include <config_cmd_default.h>
62 #undef CONFIG_CMD_NET /* disabeled - causes compile errors */
64 #define CONFIG_CMD_MEMORY
65 #define CONFIG_CMD_LOADB
66 #define CONFIG_CMD_REGINFO
67 #define CONFIG_CMD_FLASH
68 #define CONFIG_CMD_LOADS
69 #define CONFIG_CMD_ASKENV
70 #define CONFIG_CMD_BDI
71 #define CONFIG_CMD_CONSOLE
72 #define CONFIG_CMD_ENV
73 #define CONFIG_CMD_RUN
74 #define CONFIG_CMD_IMI
78 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
80 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
82 #define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */
84 #define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */
86 #define CONFIG_WATCHDOG /* turn on platform specific watchdog */
88 #define CONFIG_STATUS_LED 1 /* Enable status led */
90 #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
93 * Miscellaneous configurable options
96 #define CFG_LONGHELP /* undef to save memory */
97 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
98 #if defined(CONFIG_CMD_KGDB)
99 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
101 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
103 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
104 #define CFG_MAXARGS 16 /* max number of command args */
105 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
107 #define CFG_MEMTEST_START 0x00000000 /* memtest works on */
108 #define CFG_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */
110 #define CFG_LOAD_ADDR 0x100000 /* default load address */
112 #define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
114 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
118 * Low Level Configuration Settings
122 * Internal Memory Mapped (This is not the IMMR content)
124 #define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */
127 * Definitions for initial stack pointer and data area
129 #define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
130 #define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
131 #define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */
132 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
133 #define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
136 * Start addresses for the final memory configuration
137 * Please note that CFG_SDRAM_BASE _must_ start at 0
139 #define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
140 #define CFG_FLASH_BASE 0x02000000 /* External flash */
141 #define PLD_BASE 0x03000000 /* PLD */
142 #define ANYBUS_BASE 0x03010000 /* Anybus Module */
144 #define CFG_RESET_ADRESS 0x01000000 /* Adress which causes reset */
145 #define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */
146 /* This adress is given to the linker with -Ttext to */
147 /* locate the text section at this adress. */
148 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
149 #define CFG_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */
152 * For booting Linux, the board info and command line data
153 * have to be in the first 8 MB of memory, since this is
154 * the maximum mapped by the Linux kernel during initialization.
156 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
159 /*-----------------------------------------------------------------------
161 *-----------------------------------------------------------------------
165 #define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
166 #define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */
167 #define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
168 #define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
169 #define CFG_FLASH_PROTECTION 1 /* Physically section protection on */
171 #define CFG_ENV_IS_IN_FLASH 1
173 #ifdef CFG_ENV_IS_IN_FLASH
174 #define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
175 #define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
178 /*-----------------------------------------------------------------------
179 * SYPCR - System Protection Control
180 * SYPCR can only be written once after reset!
181 *-----------------------------------------------------------------------
184 #if defined(CONFIG_WATCHDOG)
185 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
186 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
188 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
190 #endif /* CONFIG_WATCHDOG */
192 /*-----------------------------------------------------------------------
193 * TBSCR - Time Base Status and Control
194 *-----------------------------------------------------------------------
195 * Clear Reference Interrupt Status, Timebase freezing enabled
197 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
199 /*-----------------------------------------------------------------------
200 * PISCR - Periodic Interrupt Status and Control
201 *-----------------------------------------------------------------------
202 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
204 #define CFG_PISCR (PISCR_PITF)
206 /*-----------------------------------------------------------------------
207 * SCCR - System Clock and reset Control Register
208 *-----------------------------------------------------------------------
209 * Set clock output, timebase and RTC source and divider,
210 * power management and some other internal clocks
212 #define SCCR_MASK SCCR_EBDF00
213 #define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
214 SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000)
216 /*-----------------------------------------------------------------------
217 * SIUMCR - SIU Module Configuration
218 *-----------------------------------------------------------------------
221 #define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */
223 /*-----------------------------------------------------------------------
224 * PLPRCR - PLL, Low-Power, and Reset Control Register
225 *-----------------------------------------------------------------------
226 * Set all bits to 40 Mhz
229 #define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
230 #define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
233 /*-----------------------------------------------------------------------
234 * UMCR - UIMB Module Configuration Register
235 *-----------------------------------------------------------------------
238 #define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
240 /*-----------------------------------------------------------------------
241 * ICTRL - I-Bus Support Control Register
243 #define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
245 /*-----------------------------------------------------------------------
246 * USIU - Memory Controller Register
247 *-----------------------------------------------------------------------
250 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
251 #define CFG_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3)
252 #define CFG_BR1_PRELIM (ANYBUS_BASE)
253 #define CFG_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
254 #define CFG_BR2_PRELIM (CFG_SDRAM_BASE | BR_V | BR_PS_32)
255 #define CFG_OR2_PRELIM (OR_ADDR_MK_FF)
256 #define CFG_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
257 #define CFG_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
258 OR_ACS_10 | OR_ETHR | OR_CSNT)
260 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */
262 /*-----------------------------------------------------------------------
263 * DER - Timer Decrementer
264 *-----------------------------------------------------------------------
267 #define CFG_DER 0x00000000
271 * Internal Definitions
275 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
276 #define BOOTFLAG_WARM 0x02 /* Software reboot */
278 #endif /* __CONFIG_H */