2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * Corenet DS style board configuration file
13 #include "../board/freescale/common/ics307_clk.h"
15 #ifdef CONFIG_RAMBOOT_PBL
16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
18 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
19 #if defined(CONFIG_P3041DS)
20 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg
21 #elif defined(CONFIG_P4080DS)
22 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg
23 #elif defined(CONFIG_P5020DS)
24 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg
25 #elif defined(CONFIG_P5040DS)
26 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg
30 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
31 /* Set 1M boot space */
32 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
33 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
34 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36 #define CONFIG_SYS_NO_FLASH
39 /* High Level Configuration Options */
41 #define CONFIG_E500 /* BOOKE e500 family */
42 #define CONFIG_E500MC /* BOOKE e500mc family */
43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
44 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
45 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
46 #define CONFIG_MP /* support multiple processors */
48 #ifndef CONFIG_SYS_TEXT_BASE
49 #define CONFIG_SYS_TEXT_BASE 0xeff80000
52 #ifndef CONFIG_RESET_VECTOR_ADDRESS
53 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
56 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
57 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
58 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
59 #define CONFIG_PCI /* Enable PCI/PCIE */
60 #define CONFIG_PCIE1 /* PCIE controler 1 */
61 #define CONFIG_PCIE2 /* PCIE controler 2 */
62 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
63 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
65 #define CONFIG_FSL_LAW /* Use common FSL init code */
67 #define CONFIG_ENV_OVERWRITE
69 #ifdef CONFIG_SYS_NO_FLASH
70 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
71 #define CONFIG_ENV_IS_NOWHERE
74 #define CONFIG_FLASH_CFI_DRIVER
75 #define CONFIG_SYS_FLASH_CFI
76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
79 #if defined(CONFIG_SPIFLASH)
80 #define CONFIG_SYS_EXTRA_ENV_RELOC
81 #define CONFIG_ENV_IS_IN_SPI_FLASH
82 #define CONFIG_ENV_SPI_BUS 0
83 #define CONFIG_ENV_SPI_CS 0
84 #define CONFIG_ENV_SPI_MAX_HZ 10000000
85 #define CONFIG_ENV_SPI_MODE 0
86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
88 #define CONFIG_ENV_SECT_SIZE 0x10000
89 #elif defined(CONFIG_SDCARD)
90 #define CONFIG_SYS_EXTRA_ENV_RELOC
91 #define CONFIG_ENV_IS_IN_MMC
92 #define CONFIG_FSL_FIXED_MMC_LOCATION
93 #define CONFIG_SYS_MMC_ENV_DEV 0
94 #define CONFIG_ENV_SIZE 0x2000
95 #define CONFIG_ENV_OFFSET (512 * 1097)
96 #elif defined(CONFIG_NAND)
97 #define CONFIG_SYS_EXTRA_ENV_RELOC
98 #define CONFIG_ENV_IS_IN_NAND
99 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
100 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
101 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
102 #define CONFIG_ENV_IS_IN_REMOTE
103 #define CONFIG_ENV_ADDR 0xffe20000
104 #define CONFIG_ENV_SIZE 0x2000
105 #elif defined(CONFIG_ENV_IS_NOWHERE)
106 #define CONFIG_ENV_SIZE 0x2000
108 #define CONFIG_ENV_IS_IN_FLASH
109 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
110 #define CONFIG_ENV_SIZE 0x2000
111 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
114 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
117 * These can be toggled for performance analysis, otherwise use default.
119 #define CONFIG_SYS_CACHE_STASHING
120 #define CONFIG_BACKSIDE_L2_CACHE
121 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
122 #define CONFIG_BTB /* toggle branch predition */
123 #define CONFIG_DDR_ECC
124 #ifdef CONFIG_DDR_ECC
125 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
126 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
129 #define CONFIG_ENABLE_36BIT_PHYS
131 #ifdef CONFIG_PHYS_64BIT
132 #define CONFIG_ADDR_MAP
133 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
136 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
137 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
138 #define CONFIG_SYS_MEMTEST_END 0x00400000
139 #define CONFIG_SYS_ALT_MEMTEST
140 #define CONFIG_PANIC_HANG /* do not reset board on panic */
143 * Config the L3 Cache as L3 SRAM
145 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
146 #ifdef CONFIG_PHYS_64BIT
147 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
149 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
151 #define CONFIG_SYS_L3_SIZE (1024 << 10)
152 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
154 #ifdef CONFIG_PHYS_64BIT
155 #define CONFIG_SYS_DCSRBAR 0xf0000000
156 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
160 #define CONFIG_ID_EEPROM
161 #define CONFIG_SYS_I2C_EEPROM_NXID
162 #define CONFIG_SYS_EEPROM_BUS_NUM 0
163 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
164 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
169 #define CONFIG_VERY_BIG_RAM
170 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
173 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
174 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
176 #define CONFIG_DDR_SPD
177 #define CONFIG_FSL_DDR3
179 #define CONFIG_SYS_SPD_BUS_NUM 1
180 #define SPD_EEPROM_ADDRESS1 0x51
181 #define SPD_EEPROM_ADDRESS2 0x52
182 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
183 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
186 * Local Bus Definitions
189 /* Set the local bus clock 1/8 of platform clock */
190 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
192 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
193 #ifdef CONFIG_PHYS_64BIT
194 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
196 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
199 #define CONFIG_SYS_FLASH_BR_PRELIM \
200 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
202 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
203 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
205 #define CONFIG_SYS_BR1_PRELIM \
206 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
207 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
209 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
210 #ifdef CONFIG_PHYS_64BIT
211 #define PIXIS_BASE_PHYS 0xfffdf0000ull
213 #define PIXIS_BASE_PHYS PIXIS_BASE
216 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
217 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
219 #define PIXIS_LBMAP_SWITCH 7
220 #define PIXIS_LBMAP_MASK 0xf0
221 #define PIXIS_LBMAP_SHIFT 4
222 #define PIXIS_LBMAP_ALTBANK 0x40
224 #define CONFIG_SYS_FLASH_QUIET_TEST
225 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
227 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
228 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
229 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
230 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
232 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
234 #if defined(CONFIG_RAMBOOT_PBL)
235 #define CONFIG_SYS_RAMBOOT
239 #ifdef CONFIG_NAND_FSL_ELBC
240 #define CONFIG_SYS_NAND_BASE 0xffa00000
241 #ifdef CONFIG_PHYS_64BIT
242 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
244 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
247 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
248 #define CONFIG_SYS_MAX_NAND_DEVICE 1
249 #define CONFIG_MTD_NAND_VERIFY_WRITE
250 #define CONFIG_CMD_NAND
251 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
253 /* NAND flash config */
254 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
255 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
256 | BR_PS_8 /* Port Size = 8 bit */ \
257 | BR_MS_FCM /* MSEL = FCM */ \
259 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
260 | OR_FCM_PGS /* Large Page*/ \
269 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
270 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
271 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
272 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
274 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
275 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
276 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
277 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
280 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
281 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
282 #endif /* CONFIG_NAND_FSL_ELBC */
284 #define CONFIG_SYS_FLASH_EMPTY_INFO
285 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
286 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
288 #define CONFIG_BOARD_EARLY_INIT_F
289 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
290 #define CONFIG_MISC_INIT_R
292 #define CONFIG_HWCONFIG
294 /* define to use L1 as initial stack */
295 #define CONFIG_L1_INIT_RAM
296 #define CONFIG_SYS_INIT_RAM_LOCK
297 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
298 #ifdef CONFIG_PHYS_64BIT
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
301 /* The assembler doesn't like typecast */
302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
303 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
304 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
310 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
312 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
313 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
315 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
316 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
318 /* Serial Port - controlled on board with jumper J8
322 #define CONFIG_CONS_INDEX 1
323 #define CONFIG_SYS_NS16550
324 #define CONFIG_SYS_NS16550_SERIAL
325 #define CONFIG_SYS_NS16550_REG_SIZE 1
326 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
328 #define CONFIG_SYS_BAUDRATE_TABLE \
329 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
333 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
334 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
336 /* Use the HUSH parser */
337 #define CONFIG_SYS_HUSH_PARSER
339 /* pass open firmware flat tree */
340 #define CONFIG_OF_LIBFDT
341 #define CONFIG_OF_BOARD_SETUP
342 #define CONFIG_OF_STDOUT_VIA_ALIAS
344 /* new uImage format support */
346 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
349 #define CONFIG_SYS_I2C
350 #define CONFIG_SYS_I2C_FSL
351 #define CONFIG_SYS_FSL_I2C_SPEED 400000
352 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
353 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
354 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
355 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
356 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
361 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
362 #ifdef CONFIG_PHYS_64BIT
363 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
365 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
367 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
369 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
370 #ifdef CONFIG_PHYS_64BIT
371 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
373 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
375 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
378 * for slave u-boot IMAGE instored in master memory space,
379 * PHYS must be aligned based on the SIZE
381 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
382 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
383 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
384 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
386 * for slave UCODE and ENV instored in master memory space,
387 * PHYS must be aligned based on the SIZE
389 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
390 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
391 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
393 /* slave core release by master*/
394 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
395 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
398 * SRIO_PCIE_BOOT - SLAVE
400 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
401 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
402 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
403 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
407 * eSPI - Enhanced SPI
409 #define CONFIG_FSL_ESPI
410 #define CONFIG_SPI_FLASH
411 #define CONFIG_SPI_FLASH_SPANSION
412 #define CONFIG_CMD_SF
413 #define CONFIG_SF_DEFAULT_SPEED 10000000
414 #define CONFIG_SF_DEFAULT_MODE 0
418 * Memory space is mapped 1-1, but I/O space must start from 0.
421 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
422 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
423 #ifdef CONFIG_PHYS_64BIT
424 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
425 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
427 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
428 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
430 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
431 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
432 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
433 #ifdef CONFIG_PHYS_64BIT
434 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
436 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
438 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
440 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
441 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
442 #ifdef CONFIG_PHYS_64BIT
443 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
444 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
446 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
447 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
449 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
450 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
451 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
452 #ifdef CONFIG_PHYS_64BIT
453 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
455 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
457 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
459 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
460 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
461 #ifdef CONFIG_PHYS_64BIT
462 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
463 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
465 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
466 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
468 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
469 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
470 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
471 #ifdef CONFIG_PHYS_64BIT
472 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
474 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
476 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
478 /* controller 4, Base address 203000 */
479 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
480 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
481 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
482 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
483 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
484 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
487 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
488 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
489 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
490 #ifdef CONFIG_PHYS_64BIT
491 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
493 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
495 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
496 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
497 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
498 #ifdef CONFIG_PHYS_64BIT
499 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
501 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
503 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
505 #define CONFIG_SYS_DPAA_FMAN
506 #define CONFIG_SYS_DPAA_PME
507 /* Default address of microcode for the Linux Fman driver */
508 #if defined(CONFIG_SPIFLASH)
510 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
511 * env, so we got 0x110000.
513 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
514 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
515 #elif defined(CONFIG_SDCARD)
517 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
518 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
519 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
521 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
522 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
523 #elif defined(CONFIG_NAND)
524 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
525 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
526 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
528 * Slave has no ucode locally, it can fetch this from remote. When implementing
529 * in two corenet boards, slave's ucode could be stored in master's memory
530 * space, the address can be mapped from slave TLB->slave LAW->
531 * slave SRIO or PCIE outbound window->master inbound window->
532 * master LAW->the ucode address in master's memory space.
534 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
535 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
537 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
538 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
540 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
541 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
543 #ifdef CONFIG_SYS_DPAA_FMAN
544 #define CONFIG_FMAN_ENET
545 #define CONFIG_PHYLIB_10G
546 #define CONFIG_PHY_VITESSE
547 #define CONFIG_PHY_TERANETICS
551 #define CONFIG_PCI_INDIRECT_BRIDGE
552 #define CONFIG_PCI_PNP /* do pci plug-and-play */
555 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
556 #define CONFIG_DOS_PARTITION
557 #endif /* CONFIG_PCI */
560 #ifdef CONFIG_FSL_SATA_V2
561 #define CONFIG_LIBATA
562 #define CONFIG_FSL_SATA
564 #define CONFIG_SYS_SATA_MAX_DEVICE 2
566 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
567 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
569 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
570 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
573 #define CONFIG_CMD_SATA
574 #define CONFIG_DOS_PARTITION
575 #define CONFIG_CMD_EXT2
578 #ifdef CONFIG_FMAN_ENET
579 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
580 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
581 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
582 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
583 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
585 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
586 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
587 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
588 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
589 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
591 #define CONFIG_SYS_TBIPA_VALUE 8
592 #define CONFIG_MII /* MII PHY management */
593 #define CONFIG_ETHPRIME "FM1@DTSEC1"
594 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
600 #define CONFIG_LOADS_ECHO /* echo on for serial download */
601 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
604 * Command line configuration.
606 #include <config_cmd_default.h>
608 #define CONFIG_CMD_DHCP
609 #define CONFIG_CMD_ELF
610 #define CONFIG_CMD_ERRATA
611 #define CONFIG_CMD_GREPENV
612 #define CONFIG_CMD_IRQ
613 #define CONFIG_CMD_I2C
614 #define CONFIG_CMD_MII
615 #define CONFIG_CMD_PING
616 #define CONFIG_CMD_SETEXPR
617 #define CONFIG_CMD_REGINFO
620 #define CONFIG_CMD_PCI
621 #define CONFIG_CMD_NET
627 #define CONFIG_HAS_FSL_DR_USB
628 #define CONFIG_HAS_FSL_MPH_USB
630 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
631 #define CONFIG_CMD_USB
632 #define CONFIG_USB_STORAGE
633 #define CONFIG_USB_EHCI
634 #define CONFIG_USB_EHCI_FSL
635 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
636 #define CONFIG_CMD_EXT2
640 #define CONFIG_FSL_ESDHC
641 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
642 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
643 #define CONFIG_CMD_MMC
644 #define CONFIG_GENERIC_MMC
645 #define CONFIG_CMD_EXT2
646 #define CONFIG_CMD_FAT
647 #define CONFIG_DOS_PARTITION
651 * Miscellaneous configurable options
653 #define CONFIG_SYS_LONGHELP /* undef to save memory */
654 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
655 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
656 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
657 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
658 #ifdef CONFIG_CMD_KGDB
659 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
661 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
663 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
664 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
665 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
666 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
669 * For booting Linux, the board info and command line data
670 * have to be in the first 64 MB of memory, since this is
671 * the maximum mapped by the Linux kernel during initialization.
673 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
674 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
676 #ifdef CONFIG_CMD_KGDB
677 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
678 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
682 * Environment Configuration
684 #define CONFIG_ROOTPATH "/opt/nfsroot"
685 #define CONFIG_BOOTFILE "uImage"
686 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
688 /* default location for tftp and bootm */
689 #define CONFIG_LOADADDR 1000000
691 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
693 #define CONFIG_BAUDRATE 115200
695 #ifdef CONFIG_P4080DS
696 #define __USB_PHY_TYPE ulpi
698 #define __USB_PHY_TYPE utmi
701 #define CONFIG_EXTRA_ENV_SETTINGS \
702 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
703 "bank_intlv=cs0_cs1;" \
704 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
705 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
707 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
708 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
709 "tftpflash=tftpboot $loadaddr $uboot && " \
710 "protect off $ubootaddr +$filesize && " \
711 "erase $ubootaddr +$filesize && " \
712 "cp.b $loadaddr $ubootaddr $filesize && " \
713 "protect on $ubootaddr +$filesize && " \
714 "cmp.b $loadaddr $ubootaddr $filesize\0" \
715 "consoledev=ttyS0\0" \
716 "ramdiskaddr=2000000\0" \
717 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
719 "fdtfile=p4080ds/p4080ds.dtb\0" \
723 #define CONFIG_HDBOOT \
724 "setenv bootargs root=/dev/$bdev rw " \
725 "console=$consoledev,$baudrate $othbootargs;" \
726 "tftp $loadaddr $bootfile;" \
727 "tftp $fdtaddr $fdtfile;" \
728 "bootm $loadaddr - $fdtaddr"
730 #define CONFIG_NFSBOOTCOMMAND \
731 "setenv bootargs root=/dev/nfs rw " \
732 "nfsroot=$serverip:$rootpath " \
733 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
734 "console=$consoledev,$baudrate $othbootargs;" \
735 "tftp $loadaddr $bootfile;" \
736 "tftp $fdtaddr $fdtfile;" \
737 "bootm $loadaddr - $fdtaddr"
739 #define CONFIG_RAMBOOTCOMMAND \
740 "setenv bootargs root=/dev/ram rw " \
741 "console=$consoledev,$baudrate $othbootargs;" \
742 "tftp $ramdiskaddr $ramdiskfile;" \
743 "tftp $loadaddr $bootfile;" \
744 "tftp $fdtaddr $fdtfile;" \
745 "bootm $loadaddr $ramdiskaddr $fdtaddr"
747 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
749 #ifdef CONFIG_SECURE_BOOT
750 #include <asm/fsl_secure_boot.h>
753 #endif /* __CONFIG_H */