2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
8 * Eric Benard <eric@eukrea.com>
10 * Configuration settings for the Eukrea CPU9260 board.
12 * SPDX-License-Identifier: GPL-2.0+
18 /* to be removed once maemory-map.h is fixed */
19 #define AT91_BASE_SYS 0xffffe800
20 #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
22 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
23 #define CONFIG_SYS_HZ 1000
24 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
26 #if defined(CONFIG_CPU9G20)
27 #define CONFIG_AT91SAM9G20
28 #elif defined(CONFIG_CPU9260)
29 #define CONFIG_AT91SAM9260
31 #error "Unknown board"
34 #include <asm/arch/hardware.h>
36 #define CONFIG_AT91FAMILY
37 #define CONFIG_ARCH_CPU_INIT
38 #define CONFIG_DISPLAY_CPUINFO
39 #define CONFIG_BOARD_EARLY_INIT_F
41 #define CONFIG_CMDLINE_TAG
42 #define CONFIG_SETUP_MEMORY_TAGS
43 #define CONFIG_INITRD_TAG
45 #if defined(CONFIG_NANDBOOT)
46 #define CONFIG_SKIP_LOWLEVEL_INIT
47 #define CONFIG_SYS_TEXT_BASE 0x23f00000
49 #define CONFIG_SYS_TEXT_BASE 0x00000000
53 #if defined(CONFIG_CPU9G20)
54 #define MASTER_PLL_DIV 0x01
55 #define MASTER_PLL_MUL 0x2B
56 #elif defined(CONFIG_CPU9260)
57 #define MASTER_PLL_DIV 0x09
58 #define MASTER_PLL_MUL 0x61
61 /* CKGR_MOR - enable main osc. */
62 #define CONFIG_SYS_MOR_VAL \
64 (255 << 8)) /* Main Oscillator Start-up Time */
65 #if defined(CONFIG_CPU9G20)
66 #define CONFIG_SYS_PLLAR_VAL \
67 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
68 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
69 #elif defined(CONFIG_CPU9260)
70 #define CONFIG_SYS_PLLAR_VAL \
71 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
73 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
76 #if defined(CONFIG_CPU9G20)
77 #define CONFIG_SYS_MCKR1_VAL \
78 (AT91_PMC_CSS_PLLA | \
80 AT91SAM9_PMC_MDIV_6 | \
82 #define CONFIG_SYS_MCKR2_VAL \
84 #elif defined(CONFIG_CPU9260)
85 #define CONFIG_SYS_MCKR1_VAL \
86 (AT91_PMC_CSS_SLOW | \
88 AT91SAM9_PMC_MDIV_2 | \
90 #define CONFIG_SYS_MCKR2_VAL \
91 (AT91_PMC_CSS_PLLA | \
93 AT91SAM9_PMC_MDIV_2 | \
97 /* define PDC[31:16] as DATA[31:16] */
98 #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
99 /* no pull-up for D[31:16] */
100 #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
102 /* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
103 #define CONFIG_SYS_MATRIX_EBICSA_VAL \
104 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
105 AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
108 /* SDRAMC_MR Mode register */
109 #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
110 /* SDRAMC_TR - Refresh Timer register */
111 #define CONFIG_SYS_SDRC_TR_VAL1 0x287
112 /* SDRAMC_CR - Configuration register*/
113 #if defined(CONFIG_CPU9G20)
114 #define CONFIG_SYS_SDRC_CR_VAL_64MB \
115 (AT91_SDRAMC_NC_9 | \
116 AT91_SDRAMC_NR_13 | \
118 AT91_SDRAMC_CAS_2 | \
119 AT91_SDRAMC_DBW_32 | \
120 (2 << 8) | /* Write Recovery Delay */ \
121 (9 << 12) | /* Row Cycle Delay */ \
122 (3 << 16) | /* Row Precharge Delay */ \
123 (3 << 20) | /* Row to Column Delay */ \
124 (6 << 24) | /* Active to Precharge Delay */ \
125 (10 << 28)) /* Exit Self Refresh to Active Delay */
127 #define CONFIG_SYS_SDRC_CR_VAL_128MB \
128 (AT91_SDRAMC_NC_10 | \
129 AT91_SDRAMC_NR_13 | \
131 AT91_SDRAMC_CAS_2 | \
132 AT91_SDRAMC_DBW_32 | \
133 (2 << 8) | /* Write Recovery Delay */ \
134 (9 << 12) | /* Row Cycle Delay */ \
135 (3 << 16) | /* Row Precharge Delay */ \
136 (3 << 20) | /* Row to Column Delay */ \
137 (6 << 24) | /* Active to Precharge Delay */ \
138 (10 << 28)) /* Exit Self Refresh to Active Delay */
139 #elif defined(CONFIG_CPU9260)
140 #define CONFIG_SYS_SDRC_CR_VAL_64MB \
141 (AT91_SDRAMC_NC_9 | \
142 AT91_SDRAMC_NR_13 | \
144 AT91_SDRAMC_CAS_2 | \
145 AT91_SDRAMC_DBW_32 | \
146 (2 << 8) | /* Write Recovery Delay */ \
147 (7 << 12) | /* Row Cycle Delay */ \
148 (2 << 16) | /* Row Precharge Delay */ \
149 (2 << 20) | /* Row to Column Delay */ \
150 (5 << 24) | /* Active to Precharge Delay */ \
151 (8 << 28)) /* Exit Self Refresh to Active Delay */
153 #define CONFIG_SYS_SDRC_CR_VAL_128MB \
154 (AT91_SDRAMC_NC_10 | \
155 AT91_SDRAMC_NR_13 | \
157 AT91_SDRAMC_CAS_2 | \
158 AT91_SDRAMC_DBW_32 | \
159 (2 << 8) | /* Write Recovery Delay */ \
160 (7 << 12) | /* Row Cycle Delay */ \
161 (2 << 16) | /* Row Precharge Delay */ \
162 (2 << 20) | /* Row to Column Delay */ \
163 (5 << 24) | /* Active to Precharge Delay */ \
164 (8 << 28)) /* Exit Self Refresh to Active Delay */
167 /* Memory Device Register -> SDRAM */
168 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
169 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
170 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
171 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
172 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
173 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
174 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
175 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
176 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
177 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
178 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
179 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
180 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
181 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
182 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
183 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
184 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
185 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
187 /* setup SMC0, CS0 (NOR Flash) - 16-bit */
188 #if defined(CONFIG_CPU9G20)
189 #define CONFIG_SYS_SMC0_SETUP0_VAL \
190 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
191 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
192 #define CONFIG_SYS_SMC0_PULSE0_VAL \
193 (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
194 AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
195 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
196 (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
197 #define CONFIG_SYS_SMC0_MODE0_VAL \
198 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
199 AT91_SMC_MODE_DBW_16 | \
200 AT91_SMC_MODE_TDF | \
201 AT91_SMC_MODE_TDF_CYCLE(3))
202 #elif defined(CONFIG_CPU9260)
203 #define CONFIG_SYS_SMC0_SETUP0_VAL \
204 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
205 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
206 #define CONFIG_SYS_SMC0_PULSE0_VAL \
207 (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
208 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
209 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
210 (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
211 #define CONFIG_SYS_SMC0_MODE0_VAL \
212 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
213 AT91_SMC_MODE_DBW_16 | \
214 AT91_SMC_MODE_TDF | \
215 AT91_SMC_MODE_TDF_CYCLE(2))
218 /* user reset enable */
219 #define CONFIG_SYS_RSTC_RMR_VAL \
221 AT91_RSTC_CR_PROCRST | \
222 AT91_RSTC_MR_ERSTL(1) | \
223 AT91_RSTC_MR_ERSTL(2))
225 /* Disable Watchdog */
226 #define CONFIG_SYS_WDTC_WDMR_VAL \
227 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
228 AT91_WDT_MR_WDV(0xfff) | \
229 AT91_WDT_MR_WDDIS | \
230 AT91_WDT_MR_WDD(0xfff))
235 #define CONFIG_AT91SAM9_WATCHDOG
236 #define CONFIG_AT91_GPIO
237 #define CONFIG_ATMEL_USART
238 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
239 #define CONFIG_USART_ID ATMEL_ID_SYS
241 #define CONFIG_BOOTDELAY 3
246 #define CONFIG_BOOTP_BOOTFILESIZE
247 #define CONFIG_BOOTP_BOOTPATH
248 #define CONFIG_BOOTP_GATEWAY
249 #define CONFIG_BOOTP_HOSTNAME
252 * Command line configuration.
254 #include <config_cmd_default.h>
255 #undef CONFIG_CMD_BDI
256 #undef CONFIG_CMD_IMI
257 #undef CONFIG_CMD_FPGA
258 #undef CONFIG_CMD_LOADS
259 #undef CONFIG_CMD_IMLS
261 #define CONFIG_CMD_PING
262 #define CONFIG_CMD_DHCP
263 #define CONFIG_CMD_NAND
264 #define CONFIG_CMD_USB
265 #define CONFIG_CMD_FAT
266 #define CONFIG_CMD_MII
269 #define CONFIG_NR_DRAM_BANKS 1
270 #define CONFIG_SYS_SDRAM_BASE 0x20000000
271 #if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
272 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
273 #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
275 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
276 #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
280 #define CONFIG_NAND_ATMEL
281 #define CONFIG_SYS_MAX_NAND_DEVICE 1
282 #define CONFIG_SYS_NAND_BASE 0x40000000
283 #define CONFIG_SYS_NAND_DBW_8 1
284 #define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13
285 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14
286 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
287 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
290 #if defined(CONFIG_NANDBOOT)
291 #define CONFIG_SYS_NO_FLASH
293 #define CONFIG_SYS_FLASH_CFI
294 #define CONFIG_FLASH_CFI_DRIVER
295 #define PHYS_FLASH_1 0x10000000
296 #define PHYS_FLASH_2 0x12000000
297 #define CONFIG_SYS_FLASH_BANKS_LIST \
298 { PHYS_FLASH_1, PHYS_FLASH_2 }
299 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
300 #define CONFIG_SYS_MAX_FLASH_SECT (255+4)
301 #define CONFIG_SYS_MAX_FLASH_BANKS 2
302 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
303 #define CONFIG_SYS_FLASH_EMPTY_INFO
304 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
305 #define CONFIG_SYS_FLASH_PROTECTION
306 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
312 #define CONFIG_NET_RETRY_COUNT 20
313 #define CONFIG_MACB_SEARCH_PHY
317 #define CONFIG_STATUS_LED
318 #define CONFIG_BOARD_SPECIFIC_LED
319 #define STATUS_LED_RED 0
320 #define STATUS_LED_GREEN 1
321 #define STATUS_LED_YELLOW 2
322 #define STATUS_LED_BLUE 3
324 #define STATUS_LED_BIT STATUS_LED_RED
325 #define STATUS_LED_STATE STATUS_LED_OFF
326 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
328 #define STATUS_LED_BIT1 STATUS_LED_GREEN
329 #define STATUS_LED_STATE1 STATUS_LED_OFF
330 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
332 #define STATUS_LED_BIT2 STATUS_LED_YELLOW
333 #define STATUS_LED_STATE2 STATUS_LED_OFF
334 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
336 #define STATUS_LED_BIT3 STATUS_LED_BLUE
337 #define STATUS_LED_STATE3 STATUS_LED_ON
338 #define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
340 #define STATUS_LED_BOOT STATUS_LED_BIT
342 #define CONFIG_RED_LED AT91_PIO_PORTC, 11
343 #define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
344 #define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
345 #define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
348 #define CONFIG_USB_ATMEL
349 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
350 #define CONFIG_USB_OHCI_NEW
351 #define CONFIG_DOS_PARTITION
352 #define CONFIG_SYS_USB_OHCI_CPU_INIT
353 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
354 #if defined(CONFIG_CPU9G20)
355 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
356 #elif defined(CONFIG_CPU9260)
357 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
359 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
360 #define CONFIG_USB_STORAGE
362 #define CONFIG_SYS_LOAD_ADDR 0x21000000
363 #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
365 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
366 #define CONFIG_SYS_MEMTEST_END \
367 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
369 #if defined(CONFIG_NANDBOOT)
370 #define CONFIG_SYS_USE_NANDFLASH
371 #undef CONFIG_SYS_USE_FLASH
373 #define CONFIG_SYS_USE_FLASH
374 #undef CONFIG_SYS_USE_NANDFLASH
377 #if defined(CONFIG_CPU9G20)
378 #define CONFIG_SYS_BASEDIR "cpu9G20"
379 #elif defined(CONFIG_CPU9260)
380 #define CONFIG_SYS_BASEDIR "cpu9260"
383 #if defined(CONFIG_SYS_USE_FLASH)
384 #define CONFIG_ENV_IS_IN_FLASH
385 #define CONFIG_ENV_OFFSET 0x40000
386 #define CONFIG_ENV_SECT_SIZE 0x20000
387 #define CONFIG_ENV_SIZE 0x20000
388 #define CONFIG_ENV_OVERWRITE
390 #define CONFIG_BOOTCOMMAND "run flashboot"
392 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
393 #define MTDPARTS_DEFAULT \
394 "mtdparts=physmap-flash.0:" \
396 "128k(u-boot-env)ro," \
401 #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
403 #define CONFIG_EXTRA_ENV_SETTINGS \
404 "mtdids=" MTDIDS_DEFAULT "\0" \
405 "mtdparts=" MTDPARTS_DEFAULT "\0" \
406 "partition=nand0,0\0" \
407 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
408 "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
409 "run ramargs;bootm 22000000\0" \
410 "flashboot=run ramargs;bootm 0x10060000\0" \
411 "basedir=" CONFIG_SYS_BASEDIR "\0" \
412 "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
413 "off 0x10000000 0x1003ffff;erase 0x10000000 " \
414 "0x1003ffff;cp.b 0x24000000 0x10000000 " \
416 "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
417 " 0x10060000 0x1021ffff;erase 0x10060000 " \
418 "0x1021ffff;cp.b 0x24000000 0x10060000 " \
420 "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
421 "protect off 0x10220000 0x13ffffff;erase " \
422 "0x10220000 0x13ffffff;cp.b 0x24000000 " \
423 "0x10220000 $(filesize)\0" \
425 #elif defined(CONFIG_NANDBOOT)
426 #define CONFIG_ENV_IS_IN_NAND
427 #define CONFIG_ENV_OFFSET 0x60000
428 #define CONFIG_ENV_OFFSET_REDUND 0x80000
429 #define CONFIG_ENV_SECT_SIZE 0x20000
430 #define CONFIG_ENV_SIZE 0x20000
431 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
432 #define CONFIG_ENV_OVERWRITE
434 #define CONFIG_BOOTCOMMAND "run flashboot"
436 #define MTDIDS_DEFAULT "nand0=atmel_nand"
437 #define MTDPARTS_DEFAULT \
438 "mtdparts=atmel_nand:" \
439 "128k(bootstrap)ro," \
441 "128k(u-boot-env)ro," \
442 "128k(u-boot-env2)ro," \
446 #define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
447 "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
449 #define CONFIG_EXTRA_ENV_SETTINGS \
450 "mtdids=" MTDIDS_DEFAULT "\0" \
451 "mtdparts=" MTDPARTS_DEFAULT "\0" \
452 "partition=nand0,5\0" \
453 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
454 "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
455 "run ramargs;bootm 22000000\0" \
456 "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
457 "0x200000; bootm 0x22000000\0" \
458 "basedir=" CONFIG_SYS_BASEDIR "\0" \
459 "u-boot=u-boot-eukrea-cpu9260.bin\0" \
460 "kernel=uImage-eukrea-cpu9260.bin\0" \
461 "rootfs=image-eukrea-cpu9260.ubi\0" \
462 "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
463 "nand erase 20000 40000; " \
464 "nand write ${loadaddr} 20000 40000\0" \
465 "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
466 "nand erase a0000 200000; " \
467 "nand write ${loadaddr} a0000 200000\0" \
468 "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
469 "nand erase 2a0000 fd60000; " \
470 "nand write ${loadaddr} 2a0000 ${filesize}\0"
473 #define CONFIG_BAUDRATE 115200
475 #if defined(CONFIG_CPU9G20)
476 #define CONFIG_SYS_PROMPT "CPU9G20=> "
477 #elif defined(CONFIG_CPU9260)
478 #define CONFIG_SYS_PROMPT "CPU9260=> "
480 #define CONFIG_SYS_CBSIZE 256
481 #define CONFIG_SYS_MAXARGS 16
482 #define CONFIG_SYS_PBSIZE \
483 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
484 #define CONFIG_SYS_LONGHELP
485 #define CONFIG_CMDLINE_EDITING
486 #define CONFIG_SILENT_CONSOLE
487 #define CONFIG_NETCONSOLE
490 * Size of malloc() pool
492 #define CONFIG_SYS_MALLOC_LEN \
493 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
495 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
496 GENERATED_GBL_DATA_SIZE)