2 * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
3 * Anders Larsen <alarsen@rea.de>
5 * Configuation settings for the Cogent CSB637 board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* ARM asynchronous clock */
30 #define AT91C_MAIN_CLOCK 184320000 /* from 3.6864 MHz crystal (3686400 * 50) */
31 #define AT91C_MASTER_CLOCK 46080000 /* (AT91C_MAIN_CLOCK/4) peripheral clock */
33 #define AT91_SLOW_CLOCK 32768 /* slow clock */
35 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
37 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
38 #define USE_920T_MMU 1
40 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
41 #define CONFIG_SETUP_MEMORY_TAGS 1
42 #define CONFIG_INITRD_TAG 1
44 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
45 #define CFG_USE_MAIN_OSCILLATOR 1
47 #define MC_PUIA_VAL 0x00000000
48 #define MC_PUP_VAL 0x00000000
49 #define MC_PUER_VAL 0x00000000
50 #define MC_ASR_VAL 0x00000000
51 #define MC_AASR_VAL 0x00000000
52 #define EBI_CFGR_VAL 0x00000000
53 #define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
56 #define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
57 #define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
58 #define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
61 #define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
62 #define PIOC_BSR_VAL 0x00000000
63 #define PIOC_PDR_VAL 0xFFFF0000
64 #define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
65 #define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */
66 #define SDRAM 0x20000000 /* address of the SDRAM */
67 #define SDRAM1 0x20000080 /* address of the SDRAM */
68 #define SDRAM_VAL 0x00000000 /* value written to SDRAM */
69 #define SDRC_MR_VAL 0x00000002 /* Precharge All */
70 #define SDRC_MR_VAL1 0x00000004 /* refresh */
71 #define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
72 #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
73 #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
74 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
76 * Size of malloc() pool
78 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
79 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
81 #define CONFIG_BAUDRATE 38400
83 #define CFG_AT91C_BRGR_DIVISOR 75 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
89 /* define one of these to choose the DBGU, USART0 or USART1 as console */
94 #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
96 #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
98 #define CONFIG_BOOTDELAY 3
99 /* #define CONFIG_ENV_OVERWRITE 1 */
101 #define CONFIG_COMMANDS \
108 CFG_CMD_AUTOSCRIPT | \
113 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
114 #include <cmd_confdefs.h>
116 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
117 #define SECTORSIZE 512
119 #define ADDR_COLUMN 1
121 #define ADDR_COLUMN_PAGE 3
123 #define NAND_ChipID_UNKNOWN 0x00
124 #define NAND_MAX_FLOORS 1
125 #define NAND_MAX_CHIPS 1
127 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
128 #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
130 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
131 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
133 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
135 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
136 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
137 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
138 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
139 /* the following are NOP's in our implementation */
140 #define NAND_CTL_CLRALE(nandptr)
141 #define NAND_CTL_SETALE(nandptr)
142 #define NAND_CTL_CLRCLE(nandptr)
143 #define NAND_CTL_SETCLE(nandptr)
145 #define CONFIG_NR_DRAM_BANKS 1
146 #define PHYS_SDRAM 0x20000000
147 #define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */
149 #define CFG_MEMTEST_START PHYS_SDRAM
150 #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 512*1024 - 4
151 #define CFG_ALT_MEMTEST 1
152 #define CFG_MEMTEST_SCRATCH CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 4
154 #define CONFIG_DRIVER_ETHER
155 #define CONFIG_NET_RETRY_COUNT 20
156 #undef CONFIG_AT91C_USE_RMII
158 #undef CONFIG_HAS_DATAFLASH
159 #define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
160 #define CFG_MAX_DATAFLASH_BANKS 0
161 #define CFG_MAX_DATAFLASH_PAGES 16384
162 #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
163 #define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
166 * FLASH Device configuration
168 #define PHYS_FLASH_1 0x10000000
169 #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
170 #define CFG_FLASH_BASE PHYS_FLASH_1
171 #define CFG_FLASH_CFI 1 /* flash is CFI conformant */
172 #define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
173 #define CFG_FLASH_EMPTY_INFO
174 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
175 #define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
176 #define CFG_FLASH_INCREMENT 0 /* there is only one bank */
177 #define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
178 #define CFG_MAX_FLASH_SECT 64
180 #define CFG_JFFS2_FIRST_BANK 0
181 #define CFG_JFFS2_FIRST_SECTOR 3
182 #define CFG_JFFS2_NUM_BANKS 1
184 #undef CFG_ENV_IS_IN_DATAFLASH
186 #ifdef CFG_ENV_IS_IN_DATAFLASH
187 #define CFG_ENV_OFFSET 0x20000
188 #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
189 #define CFG_ENV_SIZE 0x2000 /* 0x8000 */
191 #define CFG_ENV_IS_IN_FLASH 1
192 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after u-boot.bin */
193 #define CFG_ENV_SIZE 0x20000 /* sectors are 128K here */
194 #endif /* CFG_ENV_IS_IN_DATAFLASH */
197 #define CFG_LOAD_ADDR 0x21000000 /* default load address */
199 #define CFG_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600 }
201 #define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
202 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
203 #define CFG_MAXARGS 16 /* max number of command args */
204 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
207 /*-----------------------------------------------------------------------
208 * Board specific extension for bd_info
210 * This structure is embedded in the global bd_info (bd_t) structure
211 * and can be used by the board specific code (eg board/...)
215 /* helper variable for board environment handling
217 * env_crc_valid == 0 => uninitialised
218 * env_crc_valid > 0 => environment crc in flash is valid
219 * env_crc_valid < 0 => environment crc in flash is invalid
226 #define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
227 /* AT91C_TC_TIMER_DIV1_CLOCK */
229 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
231 #ifdef CONFIG_USE_IRQ
232 #error CONFIG_USE_IRQ not supported