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[u-boot] / include / configs / cyrus.h
1 /*
2  * Based on corenet_ds.h
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_CYRUS
11
12 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
13 #error Must call Cyrus CONFIG with a specific CPU enabled.
14 #endif
15
16 #define CONFIG_SDCARD
17 #define CONFIG_FSL_SATA_V2
18 #define CONFIG_PCIE3
19 #define CONFIG_PCIE4
20 #ifdef CONFIG_ARCH_P5020
21 #define CONFIG_SYS_FSL_RAID_ENGINE
22 #define CONFIG_SYS_DPAA_RMAN
23 #endif
24 #define CONFIG_SYS_DPAA_PME
25
26 /*
27  * Corenet DS style board configuration file
28  */
29 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
30 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
31 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
32 #if defined(CONFIG_ARCH_P5020)
33 #define CONFIG_SYS_CLK_FREQ 133000000
34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
35 #elif defined(CONFIG_ARCH_P5040)
36 #define CONFIG_SYS_CLK_FREQ 100000000
37 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
38 #endif
39
40 /* High Level Configuration Options */
41 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
42 #define CONFIG_MP                       /* support multiple processors */
43
44 #define CONFIG_SYS_MMC_MAX_DEVICE     1
45
46 #ifndef CONFIG_SYS_TEXT_BASE
47 #define CONFIG_SYS_TEXT_BASE    0xeff40000
48 #endif
49
50 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
51 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
52 #define CONFIG_PCIE1                    /* PCIE controller 1 */
53 #define CONFIG_PCIE2                    /* PCIE controller 2 */
54 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
55 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
56
57 #define CONFIG_ENV_OVERWRITE
58
59 #if defined(CONFIG_SDCARD)
60 #define CONFIG_SYS_EXTRA_ENV_RELOC
61 #define CONFIG_FSL_FIXED_MMC_LOCATION
62 #define CONFIG_SYS_MMC_ENV_DEV          0
63 #define CONFIG_ENV_SIZE                 0x2000
64 #define CONFIG_ENV_OFFSET               (512 * 1658)
65 #endif
66
67 /*
68  * These can be toggled for performance analysis, otherwise use default.
69  */
70 #define CONFIG_SYS_CACHE_STASHING
71 #define CONFIG_BACKSIDE_L2_CACHE
72 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
73 #define CONFIG_BTB                      /* toggle branch predition */
74 #define CONFIG_DDR_ECC
75 #ifdef CONFIG_DDR_ECC
76 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
77 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
78 #endif
79
80 #define CONFIG_ENABLE_36BIT_PHYS
81
82 #ifdef CONFIG_PHYS_64BIT
83 #define CONFIG_ADDR_MAP
84 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
85 #endif
86
87 /* test POST memory test */
88 #undef CONFIG_POST
89 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
90 #define CONFIG_SYS_MEMTEST_END          0x00400000
91 #define CONFIG_SYS_ALT_MEMTEST
92
93 /*
94  *  Config the L3 Cache as L3 SRAM
95  */
96 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
97 #ifdef CONFIG_PHYS_64BIT
98 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
99 #else
100 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
101 #endif
102 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
103 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
104
105 #ifdef CONFIG_PHYS_64BIT
106 #define CONFIG_SYS_DCSRBAR              0xf0000000
107 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
108 #endif
109
110 /*
111  * DDR Setup
112  */
113 #define CONFIG_VERY_BIG_RAM
114 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
115 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
116
117 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
118 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
119
120 #define CONFIG_DDR_SPD
121
122 #define CONFIG_SYS_SPD_BUS_NUM  1
123 #define SPD_EEPROM_ADDRESS1     0x51
124 #define SPD_EEPROM_ADDRESS2     0x52
125 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
126
127 /*
128  * Local Bus Definitions
129  */
130
131 #define CONFIG_SYS_LBC0_BASE            0xe0000000 /* Start of LBC Registers */
132 #ifdef CONFIG_PHYS_64BIT
133 #define CONFIG_SYS_LBC0_BASE_PHYS       0xfe0000000ull
134 #else
135 #define CONFIG_SYS_LBC0_BASE_PHYS       CONFIG_SYS_LBC0_BASE
136 #endif
137
138 #define CONFIG_SYS_LBC1_BASE            0xe1000000 /* Start of LBC Registers */
139 #ifdef CONFIG_PHYS_64BIT
140 #define CONFIG_SYS_LBC1_BASE_PHYS       0xfe1000000ull
141 #else
142 #define CONFIG_SYS_LBC1_BASE_PHYS       CONFIG_SYS_LBC1_BASE
143 #endif
144
145 /* Set the local bus clock 1/16 of platform clock */
146 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_16 | LCRR_EADC_1)
147
148 #define CONFIG_SYS_BR0_PRELIM \
149 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
150 #define CONFIG_SYS_BR1_PRELIM \
151 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
152
153 #define CONFIG_SYS_OR0_PRELIM   0xfff00010
154 #define CONFIG_SYS_OR1_PRELIM   0xfff00010
155
156 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
157
158 #if defined(CONFIG_RAMBOOT_PBL)
159 #define CONFIG_SYS_RAMBOOT
160 #endif
161
162 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
163 #define CONFIG_MISC_INIT_R
164
165 #define CONFIG_HWCONFIG
166
167 /* define to use L1 as initial stack */
168 #define CONFIG_L1_INIT_RAM
169 #define CONFIG_SYS_INIT_RAM_LOCK
170 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
171 #ifdef CONFIG_PHYS_64BIT
172 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
174 /* The assembler doesn't like typecast */
175 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
176         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
177           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
178 #else
179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
182 #endif
183 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
184
185 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
186 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
187
188 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
189 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
190
191 /* Serial Port - controlled on board with jumper J8
192  * open - index 2
193  * shorted - index 1
194  */
195 #define CONFIG_CONS_INDEX       1
196 #define CONFIG_SYS_NS16550_SERIAL
197 #define CONFIG_SYS_NS16550_REG_SIZE     1
198 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
199
200 #define CONFIG_SYS_BAUDRATE_TABLE       \
201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
202
203 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
204 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
205 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
206 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
207
208 /* I2C */
209 #define CONFIG_SYS_I2C
210 #define CONFIG_SYS_I2C_FSL
211 #define CONFIG_I2C_MULTI_BUS
212 #define CONFIG_I2C_CMD_TREE
213 #define CONFIG_SYS_FSL_I2C_SPEED                400000  /* I2C speed and slave address */
214 #define CONFIG_SYS_FSL_I2C_SLAVE                0x7F
215 #define CONFIG_SYS_FSL_I2C_OFFSET               0x118000
216 #define CONFIG_SYS_FSL_I2C2_SPEED               400000  /* I2C speed and slave address */
217 #define CONFIG_SYS_FSL_I2C2_SLAVE               0x7F
218 #define CONFIG_SYS_FSL_I2C2_OFFSET              0x118100
219 #define CONFIG_SYS_FSL_I2C3_SPEED               400000  /* I2C speed and slave address */
220 #define CONFIG_SYS_FSL_I2C3_SLAVE               0x7F
221 #define CONFIG_SYS_FSL_I2C3_OFFSET              0x119000
222 #define CONFIG_SYS_FSL_I2C4_SPEED               400000  /* I2C speed and slave address */
223 #define CONFIG_SYS_FSL_I2C4_SLAVE               0x7F
224 #define CONFIG_SYS_FSL_I2C4_OFFSET              0x119100
225
226 #define CONFIG_ID_EEPROM
227 #define CONFIG_SYS_I2C_EEPROM_NXID
228 #define CONFIG_SYS_EEPROM_BUS_NUM       0
229 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
230 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
231
232 #define CONFIG_SYS_I2C_GENERIC_MAC
233 #define CONFIG_SYS_I2C_MAC1_BUS 3
234 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
235 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
236 #define CONFIG_SYS_I2C_MAC2_BUS 0
237 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
238 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
239
240 #define CONFIG_RTC_MCP79411             1
241 #define CONFIG_SYS_RTC_BUS_NUM          3
242 #define CONFIG_SYS_I2C_RTC_ADDR         0x6f
243
244 /*
245  * eSPI - Enhanced SPI
246  */
247
248 /*
249  * General PCI
250  * Memory space is mapped 1-1, but I/O space must start from 0.
251  */
252
253 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
254 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
255 #ifdef CONFIG_PHYS_64BIT
256 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
257 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
258 #else
259 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
260 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
261 #endif
262 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
263 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
264 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
265 #ifdef CONFIG_PHYS_64BIT
266 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
267 #else
268 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
269 #endif
270 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
271
272 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
273 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
274 #ifdef CONFIG_PHYS_64BIT
275 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
276 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
277 #else
278 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
279 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
280 #endif
281 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
282 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
283 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
284 #ifdef CONFIG_PHYS_64BIT
285 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
286 #else
287 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
288 #endif
289 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
290
291 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
292 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
293 #ifdef CONFIG_PHYS_64BIT
294 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
295 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
296 #else
297 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
298 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
299 #endif
300 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
301 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
302 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
303 #ifdef CONFIG_PHYS_64BIT
304 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
305 #else
306 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
307 #endif
308 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
309
310 /* controller 4, Base address 203000 */
311 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
312 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
313 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
314 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
315 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
316 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
317
318 /* Qman/Bman */
319 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
320 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
321 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
322 #ifdef CONFIG_PHYS_64BIT
323 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
324 #else
325 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
326 #endif
327 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
328 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
329 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
330 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
331 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
332 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
333                                          CONFIG_SYS_BMAN_CENA_SIZE)
334 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
335 #define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
336 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
337 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
338 #ifdef CONFIG_PHYS_64BIT
339 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
340 #else
341 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
342 #endif
343 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
344 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
345 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
346 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
347 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
348 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
349                                           CONFIG_SYS_QMAN_CENA_SIZE)
350 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
351 #define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
352
353 #define CONFIG_SYS_DPAA_FMAN
354 /* Default address of microcode for the Linux Fman driver */
355 /*
356  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
357  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
358  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
359  */
360 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
361 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
362
363 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
364 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
365
366 #ifdef CONFIG_SYS_DPAA_FMAN
367 #define CONFIG_FMAN_ENET
368 #endif
369
370 #ifdef CONFIG_PCI
371 #define CONFIG_PCI_INDIRECT_BRIDGE
372
373 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
374 #endif  /* CONFIG_PCI */
375
376 /* SATA */
377 #ifdef CONFIG_FSL_SATA_V2
378 #define CONFIG_SYS_SATA_MAX_DEVICE      2
379 #define CONFIG_SATA1
380 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
381 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
382 #define CONFIG_SATA2
383 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
384 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
385
386 #define CONFIG_LBA48
387 #endif
388
389 #ifdef CONFIG_FMAN_ENET
390 #define CONFIG_SYS_TBIPA_VALUE  8
391 #define CONFIG_MII              /* MII PHY management */
392 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
393 #endif
394
395 /*
396  * Environment
397  */
398 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
399 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
400
401 /*
402  * USB
403  */
404 #define CONFIG_HAS_FSL_DR_USB
405 #define CONFIG_HAS_FSL_MPH_USB
406
407 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
408 #define CONFIG_USB_EHCI_FSL
409 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
410 #define CONFIG_EHCI_IS_TDI
411  /* _VIA_CONTROL_EP  */
412 #endif
413
414 #ifdef CONFIG_MMC
415 #define CONFIG_FSL_ESDHC
416 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
417 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
418 #endif
419
420 /*
421  * Miscellaneous configurable options
422  */
423 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
424 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
425 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
426 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
427
428 /*
429  * For booting Linux, the board info and command line data
430  * have to be in the first 64 MB of memory, since this is
431  * the maximum mapped by the Linux kernel during initialization.
432  */
433 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
434 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
435
436 #ifdef CONFIG_CMD_KGDB
437 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
438 #endif
439
440 /*
441  * Environment Configuration
442  */
443 #define CONFIG_ROOTPATH         "/opt/nfsroot"
444 #define CONFIG_BOOTFILE         "uImage"
445 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
446
447 /* default location for tftp and bootm */
448 #define CONFIG_LOADADDR         1000000
449
450 #define __USB_PHY_TYPE  utmi
451
452 #define CONFIG_EXTRA_ENV_SETTINGS \
453 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
454 "bank_intlv=cs0_cs1;"                                   \
455 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
456 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
457 "netdev=eth0\0"                                         \
458 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
459 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
460 "consoledev=ttyS0\0"                                    \
461 "ramdiskaddr=2000000\0"                                 \
462 "fdtaddr=1e00000\0"                                     \
463 "bdev=sda3\0"
464
465 #define CONFIG_HDBOOT                                   \
466 "setenv bootargs root=/dev/$bdev rw "           \
467 "console=$consoledev,$baudrate $othbootargs;"   \
468 "tftp $loadaddr $bootfile;"                     \
469 "tftp $fdtaddr $fdtfile;"                       \
470 "bootm $loadaddr - $fdtaddr"
471
472 #define CONFIG_NFSBOOTCOMMAND                   \
473 "setenv bootargs root=/dev/nfs rw "     \
474 "nfsroot=$serverip:$rootpath "          \
475 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
476 "console=$consoledev,$baudrate $othbootargs;"   \
477 "tftp $loadaddr $bootfile;"             \
478 "tftp $fdtaddr $fdtfile;"               \
479 "bootm $loadaddr - $fdtaddr"
480
481 #define CONFIG_RAMBOOTCOMMAND                           \
482 "setenv bootargs root=/dev/ram rw "             \
483 "console=$consoledev,$baudrate $othbootargs;"   \
484 "tftp $ramdiskaddr $ramdiskfile;"               \
485 "tftp $loadaddr $bootfile;"                     \
486 "tftp $fdtaddr $fdtfile;"                       \
487 "bootm $loadaddr $ramdiskaddr $fdtaddr"
488
489 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
490
491 #include <asm/fsl_secure_boot.h>
492
493 #ifdef CONFIG_SECURE_BOOT
494 #endif
495
496 #endif  /* __CONFIG_H */