3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_DBAU1X00 1
16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
18 #ifdef CONFIG_DBAU1000
19 /* Also known as Merlot */
20 #define CONFIG_SOC_AU1000 1
22 #ifdef CONFIG_DBAU1100
23 #define CONFIG_SOC_AU1100 1
25 #ifdef CONFIG_DBAU1500
26 #define CONFIG_SOC_AU1500 1
28 #ifdef CONFIG_DBAU1550
30 #define CONFIG_SOC_AU1550 1
32 #error "No valid board set"
40 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
42 #define CONFIG_EXTRA_ENV_SETTINGS \
43 "addmisc=setenv bootargs ${bootargs} " \
44 "console=ttyS0,${baudrate} " \
46 "bootfile=/tftpboot/vmlinux.srec\0" \
47 "load=tftp 80500000 ${u-boot}\0" \
50 #ifdef CONFIG_DBAU1550
51 /* Boot from flash by default, revert to bootp */
52 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
53 #else /* CONFIG_DBAU1550 */
54 #define CONFIG_BOOTCOMMAND "bootp;bootm"
55 #endif /* CONFIG_DBAU1550 */
60 #define CONFIG_BOOTP_BOOTFILESIZE
61 #define CONFIG_BOOTP_BOOTPATH
62 #define CONFIG_BOOTP_GATEWAY
63 #define CONFIG_BOOTP_HOSTNAME
66 * Command line configuration.
70 * Miscellaneous configurable options
72 #define CONFIG_SYS_LONGHELP /* undef to save memory */
74 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
75 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
76 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
78 #define CONFIG_SYS_MALLOC_LEN 128*1024
80 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
82 #define CONFIG_SYS_MHZ 396
84 #if (CONFIG_SYS_MHZ % 12) != 0
85 #error "Invalid CPU frequency - must be multiple of 12!"
88 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
90 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
92 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
94 #define CONFIG_SYS_MEMTEST_START 0x80100000
95 #define CONFIG_SYS_MEMTEST_END 0x80800000
97 /*-----------------------------------------------------------------------
98 * FLASH and environment organization
100 #ifdef CONFIG_DBAU1550
102 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
103 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
105 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
106 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
108 #else /* CONFIG_DBAU1550 */
110 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
111 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
113 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
114 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
116 #endif /* CONFIG_DBAU1550 */
118 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
120 #define CONFIG_SYS_FLASH_CFI 1
121 #define CONFIG_FLASH_CFI_DRIVER 1
123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
124 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
126 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
128 /* We boot from this flash, selected with dip switch */
129 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
131 /* timeout values are in ticks */
132 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
133 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
135 /* Address and size of Primary Environment Sector */
136 #define CONFIG_ENV_ADDR 0xB0030000
137 #define CONFIG_ENV_SIZE 0x10000
139 #define CONFIG_FLASH_16BIT
141 #define CONFIG_NR_DRAM_BANKS 2
143 #ifdef CONFIG_DBAU1550
149 #define CONFIG_MEMSIZE_IN_BYTES
151 #ifndef CONFIG_DBAU1550
152 /*---ATA PCMCIA ------------------------------------*/
153 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
154 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
155 #define CONFIG_PCMCIA_SLOT_A
157 #define CONFIG_ATAPI 1
159 /* We run CF in "true ide" mode or a harddrive via pcmcia */
160 #define CONFIG_IDE_PCMCIA 1
162 /* We only support one slot for now */
163 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
164 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
166 #undef CONFIG_IDE_LED /* LED for ide not supported */
167 #undef CONFIG_IDE_RESET /* reset for ide not supported */
169 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
171 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
173 /* Offset for data I/O */
174 #define CONFIG_SYS_ATA_DATA_OFFSET 8
176 /* Offset for normal register accesses */
177 #define CONFIG_SYS_ATA_REG_OFFSET 0
179 /* Offset for alternate registers */
180 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
181 #endif /* CONFIG_DBAU1550 */
183 #endif /* __CONFIG_H */