3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * This file contains the configuration parameters for the dbau1x00 board.
15 #define CONFIG_DBAU1X00 1
16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
18 #ifdef CONFIG_DBAU1000
19 /* Also known as Merlot */
20 #define CONFIG_SOC_AU1000 1
22 #ifdef CONFIG_DBAU1100
23 #define CONFIG_SOC_AU1100 1
25 #ifdef CONFIG_DBAU1500
26 #define CONFIG_SOC_AU1500 1
28 #ifdef CONFIG_DBAU1550
30 #define CONFIG_SOC_AU1550 1
32 #error "No valid board set"
40 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
42 #define CONFIG_EXTRA_ENV_SETTINGS \
43 "addmisc=setenv bootargs ${bootargs} " \
44 "console=ttyS0,${baudrate} " \
46 "bootfile=/tftpboot/vmlinux.srec\0" \
47 "load=tftp 80500000 ${u-boot}\0" \
50 #ifdef CONFIG_DBAU1550
51 /* Boot from flash by default, revert to bootp */
52 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
53 #else /* CONFIG_DBAU1550 */
54 #define CONFIG_BOOTCOMMAND "bootp;bootm"
55 #endif /* CONFIG_DBAU1550 */
60 #define CONFIG_BOOTP_BOOTFILESIZE
63 * Command line configuration.
67 * Miscellaneous configurable options
70 #define CONFIG_SYS_MALLOC_LEN 128*1024
72 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
74 #define CONFIG_SYS_MHZ 396
76 #if (CONFIG_SYS_MHZ % 12) != 0
77 #error "Invalid CPU frequency - must be multiple of 12!"
80 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
82 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
84 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
86 #define CONFIG_SYS_MEMTEST_START 0x80100000
87 #define CONFIG_SYS_MEMTEST_END 0x80800000
89 /*-----------------------------------------------------------------------
90 * FLASH and environment organization
92 #ifdef CONFIG_DBAU1550
94 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
95 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
97 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
98 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
100 #else /* CONFIG_DBAU1550 */
102 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
103 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
105 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
106 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
108 #endif /* CONFIG_DBAU1550 */
110 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
112 #define CONFIG_SYS_FLASH_CFI 1
113 #define CONFIG_FLASH_CFI_DRIVER 1
115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
116 #define CONFIG_SYS_MONITOR_LEN (192 << 10)
118 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
120 /* We boot from this flash, selected with dip switch */
121 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
123 /* timeout values are in ticks */
124 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
125 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
127 /* Address and size of Primary Environment Sector */
128 #define CONFIG_ENV_ADDR 0xB0030000
129 #define CONFIG_ENV_SIZE 0x10000
131 #define CONFIG_FLASH_16BIT
133 #define CONFIG_NR_DRAM_BANKS 2
135 #ifdef CONFIG_DBAU1550
141 #define CONFIG_MEMSIZE_IN_BYTES
143 #ifndef CONFIG_DBAU1550
144 /*---ATA PCMCIA ------------------------------------*/
145 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
146 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
147 #define CONFIG_PCMCIA_SLOT_A
149 #define CONFIG_ATAPI 1
151 /* We run CF in "true ide" mode or a harddrive via pcmcia */
152 #define CONFIG_IDE_PCMCIA 1
154 /* We only support one slot for now */
155 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
156 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
158 #undef CONFIG_IDE_RESET /* reset for ide not supported */
160 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
162 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
164 /* Offset for data I/O */
165 #define CONFIG_SYS_ATA_DATA_OFFSET 8
167 /* Offset for normal register accesses */
168 #define CONFIG_SYS_ATA_REG_OFFSET 0
170 /* Offset for alternate registers */
171 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
172 #endif /* CONFIG_DBAU1550 */
174 #endif /* __CONFIG_H */