2 * Embest/Timll DevKit3250 board configuration file
4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __CONFIG_DEVKIT3250_H__
10 #define __CONFIG_DEVKIT3250_H__
12 /* SoC and board defines */
13 #include <linux/sizes.h>
14 #include <asm/arch/cpu.h>
17 * Define DevKit3250 machine type by hand until it lands in mach-types
19 #define MACH_TYPE_DEVKIT3250 3697
20 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
22 #define CONFIG_SYS_ICACHE_OFF
23 #define CONFIG_SYS_DCACHE_OFF
24 #if !defined(CONFIG_SPL_BUILD)
25 #define CONFIG_SKIP_LOWLEVEL_INIT
27 #define CONFIG_BOARD_EARLY_INIT_F
30 * Memory configurations
32 #define CONFIG_NR_DRAM_BANKS 1
33 #define CONFIG_SYS_MALLOC_LEN SZ_1M
34 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
35 #define CONFIG_SYS_SDRAM_SIZE SZ_64M
36 #define CONFIG_SYS_TEXT_BASE 0x83FA0000
37 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
38 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
40 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
42 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
43 - GENERATED_GBL_DATA_SIZE)
48 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
49 #define CONFIG_BAUDRATE 115200
54 #define CONFIG_SYS_I2C
55 #define CONFIG_SYS_I2C_LPC32XX
56 #define CONFIG_SYS_I2C_SPEED 100000
57 #define CONFIG_CMD_I2C
62 #define CONFIG_LPC32XX_GPIO
67 #define CONFIG_LPC32XX_SSP
68 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
69 #define CONFIG_CMD_SPI
75 #define CONFIG_PHY_SMSC
76 #define CONFIG_LPC32XX_ETH
78 #define CONFIG_PHY_ADDR 0x1F
79 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
80 #define CONFIG_CMD_MII
81 #define CONFIG_CMD_PING
82 #define CONFIG_CMD_DHCP
87 #define CONFIG_SYS_MAX_FLASH_BANKS 1
88 #define CONFIG_SYS_MAX_FLASH_SECT 71
89 #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
90 #define CONFIG_SYS_FLASH_SIZE SZ_4M
91 #define CONFIG_SYS_FLASH_CFI
96 #define CONFIG_NAND_LPC32XX_SLC
97 #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
98 #define CONFIG_SYS_MAX_NAND_DEVICE 1
99 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
104 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
105 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
106 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
107 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
108 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14
109 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
110 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
111 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
113 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
114 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
115 #define CONFIG_SYS_NAND_USE_FLASH_BBT
117 #define CONFIG_CMD_NAND
120 * U-Boot General Configurations
122 #define CONFIG_SYS_LONGHELP
123 #define CONFIG_SYS_CBSIZE 1024
124 #define CONFIG_SYS_PBSIZE \
125 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
126 #define CONFIG_SYS_MAXARGS 16
127 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
129 #define CONFIG_AUTO_COMPLETE
130 #define CONFIG_CMDLINE_EDITING
131 #define CONFIG_VERSION_VARIABLE
132 #define CONFIG_DISPLAY_CPUINFO
133 #define CONFIG_DOS_PARTITION
136 * Pass open firmware flat tree
138 #define CONFIG_OF_LIBFDT
143 #define CONFIG_ENV_IS_IN_NAND 1
144 #define CONFIG_ENV_SIZE SZ_128K
145 #define CONFIG_ENV_OFFSET 0x000A0000
147 #define CONFIG_BOOTCOMMAND \
149 "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \
150 "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \
151 "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \
152 "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \
153 "bootm ${loadaddr} - ${dtbaddr}"
155 #define CONFIG_EXTRA_ENV_SETTINGS \
157 "ethaddr=00:01:90:00:C0:81\0" \
158 "dtbaddr=0x81000000\0" \
159 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
160 "tftpdir=vladimir/oe/devkit3250\0" \
161 "userargs=oops=panic\0"
166 #define CONFIG_CMD_CACHE
171 #define CONFIG_CMDLINE_TAG
172 #define CONFIG_SETUP_MEMORY_TAGS
173 #define CONFIG_ZERO_BOOTDELAY_CHECK
174 #define CONFIG_BOOTDELAY 1
176 #define CONFIG_BOOTFILE "uImage"
177 #define CONFIG_BOOTARGS "console=ttyS0,115200n8"
178 #define CONFIG_LOADADDR 0x80008000
181 * SPL specific defines
183 /* SPL will be executed at offset 0 */
184 #define CONFIG_SPL_TEXT_BASE 0x00000000
186 /* SPL will use SRAM as stack */
187 #define CONFIG_SPL_STACK 0x0000FFF8
188 #define CONFIG_SPL_BOARD_INIT
190 /* Use the framework and generic lib */
191 #define CONFIG_SPL_FRAMEWORK
192 #define CONFIG_SPL_LIBGENERIC_SUPPORT
193 #define CONFIG_SPL_LIBCOMMON_SUPPORT
195 /* SPL will use serial */
196 #define CONFIG_SPL_SERIAL_SUPPORT
198 /* SPL loads an image from NAND */
199 #define CONFIG_SPL_NAND_SIMPLE
200 #define CONFIG_SPL_NAND_RAW_ONLY
201 #define CONFIG_SPL_NAND_SUPPORT
202 #define CONFIG_SPL_NAND_DRIVERS
204 #define CONFIG_SPL_NAND_ECC
205 #define CONFIG_SPL_NAND_SOFTECC
207 #define CONFIG_SPL_MAX_SIZE 0x20000
208 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
210 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
211 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
212 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
214 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
215 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
217 /* See common/spl/spl.c spl_set_header_raw_uboot() */
218 #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
221 * Include SoC specific configuration
223 #include <asm/arch/config.h>
225 #endif /* __CONFIG_DEVKIT3250_H__*/