2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2005-2007
6 * Modified for InterControl digsyMTC MPC5200 board by
7 * Frank Bodammer, GCD Hard- & Software GmbH,
8 * frank.bodammer@gcd-solutions.de
10 * (C) Copyright 2009 Semihalf
11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software\; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation\; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY\; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program\; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 * High Level Configuration Options
39 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
40 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
41 #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
44 * Valid values for CONFIG_SYS_TEXT_BASE are:
45 * 0xFFF00000 boot high (standard configuration)
47 * 0x00100000 boot from RAM (for testing only)
49 #ifndef CONFIG_SYS_TEXT_BASE
50 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
53 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000
55 #define CONFIG_SYS_CACHELINE_SIZE 32
58 * Serial console configuration
60 #define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
61 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
62 #define CONFIG_SYS_BAUDRATE_TABLE \
63 { 9600, 19200, 38400, 57600, 115200, 230400 }
67 * 0x40000000 - 0x4fffffff - PCI Memory
68 * 0x50000000 - 0x50ffffff - PCI IO Space
71 #define CONFIG_PCI_PNP 1
72 #define CONFIG_PCI_SCAN_SHOW 1
74 #define CONFIG_PCI_MEM_BUS 0x40000000
75 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
76 #define CONFIG_PCI_MEM_SIZE 0x10000000
78 #define CONFIG_PCI_IO_BUS 0x50000000
79 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
80 #define CONFIG_PCI_IO_SIZE 0x01000000
85 #define CONFIG_DOS_PARTITION
94 #define CONFIG_VIDEO_MB862xx
95 #define CONFIG_VIDEO_MB862xx_ACCEL
96 #define CONFIG_VIDEO_CORALP
97 #define CONFIG_CFB_CONSOLE
98 #define CONFIG_VIDEO_LOGO
99 #define CONFIG_VIDEO_BMP_LOGO
100 #define CONFIG_VIDEO_SW_CURSOR
101 #define CONFIG_VGA_AS_SINGLE_DEVICE
102 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
103 #define CONFIG_SPLASH_SCREEN
104 #define CONFIG_VIDEO_BMP_GZIP
105 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
107 /* Coral-PA clock frequency, geo and other both 133MHz */
108 #define CONFIG_SYS_MB862xx_CCF 0x00050000
109 /* Video SDRAM parameters */
110 #define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
114 * Command line configuration.
116 #include <config_cmd_default.h>
119 #define CONFIG_CMD_BMP
121 #define CONFIG_CMD_DFL
122 #define CONFIG_CMD_CACHE
123 #define CONFIG_CMD_DATE
124 #define CONFIG_CMD_DHCP
125 #define CONFIG_CMD_DIAG
126 #define CONFIG_CMD_EEPROM
127 #define CONFIG_CMD_ELF
128 #define CONFIG_CMD_EXT2
129 #define CONFIG_CMD_FAT
130 #define CONFIG_CMD_I2C
131 #define CONFIG_CMD_IDE
132 #define CONFIG_CMD_IRQ
133 #define CONFIG_CMD_MII
134 #define CONFIG_CMD_PCI
135 #define CONFIG_CMD_PING
136 #define CONFIG_CMD_REGINFO
137 #define CONFIG_CMD_SAVES
138 #define CONFIG_CMD_SPI
139 #define CONFIG_CMD_USB
141 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
142 #define CONFIG_SYS_LOWBOOT 1
148 #define CONFIG_BOOTDELAY 1
150 #undef CONFIG_BOOTARGS
152 #define CONFIG_EXTRA_ENV_SETTINGS \
153 "fw_image=digsyMPC.img\0" \
154 "mtcb_start=mtc led diag orange; run mtcb_1\0" \
155 "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
156 "do mtc led $x; done\0" \
157 "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
158 "else run mtcb_fw; fi\0" \
159 "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
160 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
161 "mtcb_update=mtc led user1 orange;" \
162 "while mtc key; do ; done; run mtcb_2;\0" \
163 "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
164 "mtcb_usb1=if fatload usb 0 400000 script.img; " \
165 "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
166 "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
167 "then run mtcb_dousb; else run mtcb_ide; fi\0" \
168 "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
169 "run mtcb_wait_flickr mtcb_ds_1;\0" \
170 "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
171 "source 400000; else run mtcb_error; fi\0" \
172 "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
173 "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
174 "else run mtcb_error; fi\0" \
175 "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
176 "run mtcb_checkfw\0" \
177 "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
178 "else run mtcb_error; fi\0" \
179 "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
180 "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
181 "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
182 "mtcb_uledflckr=mtc led user1 orange 11\0" \
183 "mtcb_error=mtc led user1 red\0" \
184 "mtcb_clear=erase ff000000 ff0fffff\0" \
185 "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
186 "mtcb_success=mtc led user1 green\0" \
187 "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
188 "then run mtcb_doide; else run mtcb_error; fi\0" \
189 "mtcb_doide=mtc led user2 green 1;" \
190 "run mtcb_wait_flickr mtcb_di_1;\0" \
191 "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
192 "else run mtcb_error; fi\0" \
193 "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
194 "ramdisk_num_sector=16\0" \
195 "flash_base=ff000000\0" \
196 "flashdisk_size=e00000\0" \
197 "env_sector=fff60000\0" \
198 "flashdisk_start=ff100000\0" \
199 "load_cmd=tftp 400000 digsyMPC.img\0" \
200 "clear_cmd=erase ff000000 ff0fffff\0" \
201 "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
202 "update_cmd=run load_cmd; " \
204 "run clear_cmd flash_cmd; " \
205 "iminfo ff000000\0" \
207 "spi_watchdog=no\0" \
209 "ftps_user1=admin\0" \
210 "ftps_pass1=admin\0" \
214 "plc_sio_baud=57600\0" \
215 "plc_sio_parity=no\0" \
218 "plc_eth_srv=yes\0" \
219 "plc_eth_port=1200\0" \
223 "plc_can1_routing=no\0" \
224 "plc_can1_baudrate=250\0" \
225 "plc_can2_routing=no\0" \
226 "plc_can2_baudrate=250\0" \
227 "plc_can3_routing=no\0" \
228 "plc_can3_baudrate=250\0" \
229 "plc_can4_routing=no\0" \
230 "plc_can4_baudrate=250\0" \
232 "console=ttyPSC0\0" \
233 "kernel_addr_r=400000\0" \
234 "fdt_addr_r=600000\0" \
235 "nfsargs=setenv bootargs root=/dev/nfs rw " \
236 "nfsroot=${serverip}:${rootpath}\0" \
237 "addip=setenv bootargs ${bootargs} " \
238 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
239 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
240 "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
241 "rootpath=/opt/eldk/ppc_6xx\0" \
242 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
243 "tftp ${fdt_addr_r} ${fdt_file};" \
244 "run nfsargs addip addcons;" \
245 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
246 "load=tftp 200000 ${u-boot}\0" \
247 "update=protect off FFF00000 +${filesize};" \
248 "erase FFF00000 +${filesize};" \
249 "cp.b 200000 FFF00000 ${filesize};" \
250 "protect on FFF00000 +${filesize}\0" \
253 #define CONFIG_BOOTCOMMAND "run mtcb_start"
258 #define CONFIG_HARD_SPI 1
259 #define CONFIG_MPC52XX_SPI 1
264 #define CONFIG_HARD_I2C 1
265 #define CONFIG_SYS_I2C_MODULE 1
266 #define CONFIG_SYS_I2C_SPEED 100000
267 #define CONFIG_SYS_I2C_SLAVE 0x7F
270 * EEPROM configuration
272 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
273 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
274 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
275 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
280 #if defined(CONFIG_DIGSY_REV5)
281 #define CONFIG_SYS_I2C_RTC_ADDR 0x56
282 #define CONFIG_RTC_RV3029
283 /* Enable 5k Ohm trickle charge resistor */
284 #define CONFIG_SYS_RV3029_TCR 0x20
286 #define CONFIG_RTC_DS1337
287 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
288 #define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
291 /* ExBo I2C Addresses */
292 #if defined(CONFIG_DIGSY_REV5)
293 #define CONFIG_SYS_EXBO_EE_I2C_ADDRESS 0x54
295 #define CONFIG_SYS_EXBO_EE_I2C_ADDRESS 0x56
299 * Flash configuration
301 #define CONFIG_SYS_FLASH_CFI 1
302 #define CONFIG_FLASH_CFI_DRIVER 1
304 #if defined(CONFIG_DIGSY_REV5)
305 #define CONFIG_SYS_FLASH_BASE 0xFE000000
306 #define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
307 #define CONFIG_SYS_MAX_FLASH_BANKS 2
308 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
309 CONFIG_SYS_FLASH_BASE_CS1}
310 #define CONFIG_SYS_UPDATE_FLASH_SIZE
311 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
313 #define CONFIG_SYS_FLASH_BASE 0xFF000000
314 #define CONFIG_SYS_MAX_FLASH_BANKS 1
315 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
318 #define CONFIG_SYS_MAX_FLASH_SECT 256
319 #define CONFIG_FLASH_16BIT
320 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
321 #define CONFIG_SYS_FLASH_SIZE 0x01000000
322 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000
323 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
325 #define CONFIG_OF_LIBFDT 1
326 #define CONFIG_OF_BOARD_SETUP 1
328 #define OF_CPU "PowerPC,5200@0"
329 #define OF_SOC "soc5200@f0000000"
330 #define OF_TBCLK (bd->bi_busfreq / 4)
332 #define CONFIG_BOARD_EARLY_INIT_R
333 #define CONFIG_MISC_INIT_R
336 * Environment settings
338 #define CONFIG_ENV_IS_IN_FLASH 1
339 #if defined(CONFIG_LOWBOOT)
340 #define CONFIG_ENV_ADDR 0xFF060000
341 #else /* CONFIG_LOWBOOT */
342 #define CONFIG_ENV_ADDR 0xFFF60000
343 #endif /* CONFIG_LOWBOOT */
344 #define CONFIG_ENV_SIZE 0x10000
345 #define CONFIG_ENV_SECT_SIZE 0x20000
346 #define CONFIG_ENV_OVERWRITE 1
351 #define CONFIG_SYS_MBAR 0xF0000000
352 #define CONFIG_SYS_SDRAM_BASE 0x00000000
353 #if !defined(CONFIG_SYS_LOWBOOT)
354 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
356 #define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
360 * Use SRAM until RAM will be available
362 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
363 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
365 #define CONFIG_SYS_GBL_DATA_OFFSET \
366 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
367 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
369 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
370 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
371 #define CONFIG_SYS_RAMBOOT 1
374 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
375 #define CONFIG_SYS_MALLOC_LEN (4096 << 10)
376 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
379 * Ethernet configuration
381 #define CONFIG_MPC5xxx_FEC 1
382 #define CONFIG_MPC5xxx_FEC_MII100
383 #if defined(CONFIG_DIGSY_REV5)
384 #define CONFIG_PHY_ADDR 0x01
386 #define CONFIG_PHY_ADDR 0x00
388 #define CONFIG_PHY_RESET_DELAY 1000
390 #define CONFIG_NETCONSOLE /* include NetConsole support */
394 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
395 * Bit 0 (mask 0x80000000) : 0x1
396 * SPI on Tmr2/3/4/5 pins
397 * Bit 2:3 (mask 0x30000000) : 0x2
398 * ATA cs0/1 on csb_4/5
399 * Bit 6:7 (mask 0x03000000) : 0x2
400 * Ethernet 100Mbit with MD
401 * Bits 12:15 (mask 0x000f0000): 0x5
403 * Bits 18:19 (mask 0x00003000) : 0x2
404 * PSC3 - USB2 on PSC3
405 * Bits 20:23 (mask 0x00000f00) : 0x1
406 * PSC2 - CAN1&2 on PSC2 pins
407 * Bits 25:27 (mask 0x00000070) : 0x1
408 * PSC1 - AC97 functionality
409 * Bits 29:31 (mask 0x00000007) : 0x2
411 #define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
414 * Miscellaneous configurable options
416 #define CONFIG_SYS_LONGHELP
417 #define CONFIG_AUTO_COMPLETE 1
418 #define CONFIG_CMDLINE_EDITING 1
419 #define CONFIG_SYS_PROMPT "=> "
420 #define CONFIG_SYS_HUSH_PARSER
421 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
423 #define CONFIG_AUTOBOOT_KEYED
424 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
425 #define CONFIG_AUTOBOOT_DELAY_STR " "
427 #define CONFIG_LOOPW 1
428 #define CONFIG_MX_CYCLIC 1
429 #define CONFIG_ZERO_BOOTDELAY_CHECK
431 #define CONFIG_SYS_CBSIZE 1024
432 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
433 #define CONFIG_SYS_MAXARGS 32
434 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
436 #define CONFIG_SYS_ALT_MEMTEST
437 #define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
438 #define CONFIG_SYS_MEMTEST_START 0x00010000
439 #define CONFIG_SYS_MEMTEST_END 0x019fffff
441 #define CONFIG_SYS_LOAD_ADDR 0x00100000
443 #define CONFIG_SYS_HZ 1000
446 * Various low-level settings
448 #define CONFIG_SYS_SDRAM_CS1 1
449 #define CONFIG_SYS_XLB_PIPELINING 1
451 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
452 #define CONFIG_SYS_HID0_FINAL HID0_ICE
454 #if defined(CONFIG_SYS_LOWBOOT)
455 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
456 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
457 #define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
460 #define CONFIG_SYS_CS4_START 0x60000000
461 #define CONFIG_SYS_CS4_SIZE 0x1000
462 #define CONFIG_SYS_CS4_CFG 0x0008FC00
464 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
465 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
466 #define CONFIG_SYS_CS0_CFG 0x0002DD00
468 #if defined(CONFIG_DIGSY_REV5)
469 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
470 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
471 #define CONFIG_SYS_CS1_CFG 0x0002DD00
474 #define CONFIG_SYS_CS_BURST 0x00000000
475 #define CONFIG_SYS_CS_DEADCYCLE 0x11111111
477 #if !defined(CONFIG_SYS_LOWBOOT)
478 #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
480 #define CONFIG_SYS_RESET_ADDRESS 0xff000100
486 #define CONFIG_USB_OHCI_NEW
487 #define CONFIG_SYS_OHCI_BE_CONTROLLER
488 #define CONFIG_USB_STORAGE
490 #define CONFIG_USB_CLOCK 0x00013333
491 #define CONFIG_USB_CONFIG 0x00002000
493 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
494 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
495 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
496 #define CONFIG_SYS_USB_OHCI_CPU_INIT
501 #define CONFIG_IDE_RESET
502 #define CONFIG_IDE_PREINIT
504 #define CONFIG_SYS_ATA_CS_ON_I2C2
505 #define CONFIG_SYS_IDE_MAXBUS 1
506 #define CONFIG_SYS_IDE_MAXDEVICE 1
508 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
509 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
510 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
511 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
512 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
513 #define CONFIG_SYS_ATA_STRIDE 4
515 #define CONFIG_ATAPI 1
516 #define CONFIG_LBA48 1
518 #endif /* __CONFIG_H */