3 * Texas Instruments Incorporated.
4 * Lokesh Vutla <lokeshvutla@ti.com>
6 * Configuration settings for the TI DRA7XX board.
7 * See ti_omap5_common.h for omap5 common settings.
9 * SPDX-License-Identifier: GPL-2.0+
12 #ifndef __CONFIG_DRA7XX_EVM_H
13 #define __CONFIG_DRA7XX_EVM_H
15 #include <environment/ti/dfu.h>
18 #define CONFIG_BOARD_EARLY_INIT_F
20 #ifdef CONFIG_SPL_BUILD
21 #define CONFIG_IODELAY_RECALIBRATION
24 #define CONFIG_VERY_BIG_RAM
25 #define CONFIG_NR_DRAM_BANKS 2
26 #define CONFIG_MAX_MEM_MAPPED 0x80000000
28 #ifndef CONFIG_QSPI_BOOT
29 /* MMC ENV related defines */
30 #define CONFIG_ENV_IS_IN_MMC
31 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
32 #define CONFIG_ENV_SIZE (128 << 10)
33 #define CONFIG_ENV_OFFSET 0xE0000
34 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
35 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
38 #if (CONFIG_CONS_INDEX == 1)
39 #define CONSOLEDEV "ttyO0"
40 #elif (CONFIG_CONS_INDEX == 3)
41 #define CONSOLEDEV "ttyO2"
43 #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
44 #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
45 #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
46 #define CONFIG_BAUDRATE 115200
48 #define CONFIG_SYS_OMAP_ABE_SYSCK
50 #ifndef CONFIG_SPL_BUILD
51 /* Define the default GPT table for eMMC */
52 #define PARTS_DEFAULT \
53 /* Linux partitions */ \
54 "uuid_disk=${uuid_gpt_disk};" \
55 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
56 /* Android partitions */ \
57 "partitions_android=" \
58 "uuid_disk=${uuid_gpt_disk};" \
59 "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \
60 "name=bootloader,size=768K,uuid=${uuid_gpt_bootloader};" \
61 "name=environment,size=128K,uuid=${uuid_gpt_environment};" \
62 "name=misc,size=128K,uuid=${uuid_gpt_misc};" \
63 "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \
64 "name=efs,size=16M,uuid=${uuid_gpt_efs};" \
65 "name=crypto,size=16K,uuid=${uuid_gpt_crypto};" \
66 "name=recovery,size=10M,uuid=${uuid_gpt_recovery};" \
67 "name=boot,size=10M,uuid=${uuid_gpt_boot};" \
68 "name=system,size=768M,uuid=${uuid_gpt_system};" \
69 "name=cache,size=256M,uuid=${uuid_gpt_cache};" \
70 "name=ipu1,size=1M,uuid=${uuid_gpt_ipu1};" \
71 "name=ipu2,size=1M,uuid=${uuid_gpt_ipu2};" \
72 "name=userdata,size=-,uuid=${uuid_gpt_userdata}"
75 "dfu_bufsiz=0x10000\0" \
81 /* Discard fastboot in SPL build, to spare some space */
82 #undef CONFIG_FASTBOOT
83 #undef CONFIG_USB_FUNCTION_FASTBOOT
84 #undef CONFIG_CMD_FASTBOOT
85 #undef CONFIG_ANDROID_BOOT_IMAGE
86 #undef CONFIG_FASTBOOT_BUF_ADDR
87 #undef CONFIG_FASTBOOT_BUF_SIZE
88 #undef CONFIG_FASTBOOT_FLASH
91 #ifdef CONFIG_SPL_BUILD
92 #undef CONFIG_CMD_BOOTD
93 #ifdef CONFIG_SPL_DFU_SUPPORT
94 #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
96 "dfu_bufsiz=0x10000\0" \
101 #include <configs/ti_omap5_common.h>
103 /* Enhance our eMMC support / experience. */
104 #define CONFIG_CMD_GPT
105 #define CONFIG_EFI_PARTITION
106 #define CONFIG_RANDOM_UUID
107 #define CONFIG_HSMMC2_8BIT
110 #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
111 #define CONFIG_BOOTP_DNS2
112 #define CONFIG_BOOTP_SEND_HOSTNAME
113 #define CONFIG_BOOTP_GATEWAY
114 #define CONFIG_BOOTP_SUBNETMASK
115 #define CONFIG_NET_RETRY_COUNT 10
116 #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
117 #define CONFIG_MII /* Required in net/eth.c */
118 #define CONFIG_PHY_GIGE /* per-board part of CPSW */
119 #define CONFIG_PHYLIB
120 #define CONFIG_PHY_TI
123 #undef CONFIG_OMAP3_SPI
124 #define CONFIG_TI_SPI_MMAP
125 #define CONFIG_SF_DEFAULT_SPEED 76800000
126 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
127 #define CONFIG_QSPI_QUAD_SUPPORT
129 #ifdef CONFIG_SPL_BUILD
131 #undef CONFIG_DM_SPI_FLASH
135 * Default to using SPI for environment, etc.
136 * 0x000000 - 0x040000 : QSPI.SPL (256KiB)
137 * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
138 * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
139 * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
140 * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
141 * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
142 * 0x9E0000 - 0x2000000 : USERLAND
144 #define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
145 #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
146 #define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
147 #if defined(CONFIG_QSPI_BOOT)
148 #define CONFIG_ENV_IS_IN_SPI_FLASH
149 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
150 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
151 #define CONFIG_ENV_SIZE (64 << 10)
152 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
153 #define CONFIG_ENV_OFFSET 0x1C0000
154 #define CONFIG_ENV_OFFSET_REDUND 0x1D0000
158 #define CONFIG_TI_EDMA3
159 #define CONFIG_SPL_SPI_LOAD
160 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
162 #define CONFIG_SUPPORT_EMMC_BOOT
165 #define CONFIG_USB_XHCI_OMAP
166 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
168 #define CONFIG_OMAP_USB_PHY
169 #define CONFIG_OMAP_USB2PHY2_HOST
172 #define CONFIG_BOARD_LATE_INIT
174 #define CONFIG_LIBATA
175 #define CONFIG_SCSI_AHCI
176 #define CONFIG_SCSI_AHCI_PLAT
177 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
178 #define CONFIG_SYS_SCSI_MAX_LUN 1
179 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
180 CONFIG_SYS_SCSI_MAX_LUN)
184 /* NAND: device related configs */
185 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
186 #define CONFIG_SYS_NAND_OOBSIZE 64
187 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
188 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
189 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
190 CONFIG_SYS_NAND_PAGE_SIZE)
191 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
192 /* NAND: driver related configs */
193 #define CONFIG_NAND_OMAP_GPMC
194 #define CONFIG_NAND_OMAP_ELM
195 #define CONFIG_SYS_NAND_ONFI_DETECTION
196 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
197 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
198 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
199 10, 11, 12, 13, 14, 15, 16, 17, \
200 18, 19, 20, 21, 22, 23, 24, 25, \
201 26, 27, 28, 29, 30, 31, 32, 33, \
202 34, 35, 36, 37, 38, 39, 40, 41, \
203 42, 43, 44, 45, 46, 47, 48, 49, \
204 50, 51, 52, 53, 54, 55, 56, 57, }
205 #define CONFIG_SYS_NAND_ECCSIZE 512
206 #define CONFIG_SYS_NAND_ECCBYTES 14
207 #define MTDIDS_DEFAULT "nand0=nand.0"
208 #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
210 "128k(NAND.SPL.backup1)," \
211 "128k(NAND.SPL.backup2)," \
212 "128k(NAND.SPL.backup3)," \
213 "256k(NAND.u-boot-spl-os)," \
215 "128k(NAND.u-boot-env)," \
216 "128k(NAND.u-boot-env.backup1)," \
218 "-(NAND.file-system)"
219 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
220 /* NAND: SPL related configs */
221 #ifdef CONFIG_SPL_NAND_SUPPORT
222 #define CONFIG_SPL_NAND_AM33XX_BCH
224 /* NAND: SPL falcon mode configs */
225 #ifdef CONFIG_SPL_OS_BOOT
226 #define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os-boot params*/
227 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
228 #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
230 #endif /* !CONFIG_NAND */
232 /* Parallel NOR Support */
233 #if defined(CONFIG_NOR)
234 /* NOR: device related configs */
235 #define CONFIG_SYS_MAX_FLASH_SECT 512
236 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
237 #define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */
238 /* #define CONFIG_INIT_IGNORE_ERROR */
239 #undef CONFIG_SYS_NO_FLASH
240 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
241 #define CONFIG_SYS_FLASH_PROTECTION
242 #define CONFIG_SYS_FLASH_CFI
243 #define CONFIG_FLASH_CFI_DRIVER
244 #define CONFIG_FLASH_CFI_MTD
245 #define CONFIG_SYS_MAX_FLASH_BANKS 1
246 #define CONFIG_SYS_FLASH_BASE (0x08000000)
247 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
248 /* Reduce SPL size by removing unlikey targets */
249 #ifdef CONFIG_NOR_BOOT
250 #define CONFIG_ENV_IS_IN_FLASH
251 #define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */
252 #define MTDIDS_DEFAULT "nor0=physmap-flash.0"
253 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
255 "128k(NOR.SPL.backup1)," \
256 "128k(NOR.SPL.backup2)," \
257 "128k(NOR.SPL.backup3)," \
258 "256k(NOR.u-boot-spl-os)," \
260 "128k(NOR.u-boot-env)," \
261 "128k(NOR.u-boot-env.backup1)," \
264 #define CONFIG_ENV_OFFSET 0x001c0000
265 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000
267 #endif /* NOR support */
270 #define CONFIG_EEPROM_CHIP_ADDRESS 0x50
271 #define CONFIG_EEPROM_BUS_ADDRESS 0
273 #endif /* __CONFIG_DRA7XX_EVM_H */