2 * (C) Copyright 2008-2009
3 * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
4 * Jens Scharsig <esw@bus-elektronik.de>
6 * Configuation settings for the EB+CPUx9K2 board.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #ifndef _CONFIG_EB_CPUx9K2_H_
28 #define _CONFIG_EB_CPUx9K2_H_
30 /*--------------------------------------------------------------------------*/
32 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
33 #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
34 #define CONFIG_EB_CPUX9K2 1 /* on an EP+CPUX9K2 Board */
35 #define USE_920T_MMU 1
37 #define CONFIG_VERSION_VARIABLE 1
38 #define CONFIG_IDENT_STRING " on EB+CPUx9K2"
40 #include <asm/arch/hardware.h> /* needed for port definitions */
42 #define CONFIG_MISC_INIT_R
44 /*--------------------------------------------------------------------------*/
45 #define CONFIG_SYS_TEXT_BASE 0x00000000
46 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
48 #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
49 #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
50 #define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
53 #define CONFIG_BOOT_RETRY_TIME 30
54 #define CONFIG_CMDLINE_EDITING
56 #define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
57 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
58 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
59 #define CONFIG_SYS_PBSIZE \
60 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
62 #define CONFIG_STACKSIZE (32*1024) /* regular stack */
65 * ARM asynchronous clock
68 #define AT91C_MAIN_CLOCK 179404800 /* from 12.288 MHz * 73 / 5 */
69 #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3)
70 #define CONFIG_SYS_HZ 1000
71 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
73 #define AT91_SLOW_CLOCK 32768 /* slow clock */
75 #define CONFIG_CMDLINE_TAG 1
76 #define CONFIG_SETUP_MEMORY_TAGS 1
77 #define CONFIG_INITRD_TAG 1
79 #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
81 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
82 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
85 #define CONFIG_SYS_PLLAR_VAL 0x20483E05 /* 179.4048 MHz for PCK */
86 #define CONFIG_SYS_PLLBR_VAL 0x104C3E0A /* 47.3088 MHz (for USB) */
87 #define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Clock */
90 * Size of malloc() pool
93 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 520*1024)
94 #define CONFIG_SYS_GBL_DATA_SIZE 128
100 #define CONFIG_NR_DRAM_BANKS 1
102 #define CONFIG_SYS_SDRAM_BASE 0x20000000
103 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
104 #define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */
106 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
107 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
108 CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
109 CONFIG_SYS_MALLOC_LEN)
111 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */
112 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
113 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
114 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
115 #define CONFIG_SYS_SDRC_CR_VAL 0x2188c159 /* set up the SDRAM */
116 #define CONFIG_SYS_SDRAM 0x20000000 /* address of the SDRAM */
117 #define CONFIG_SYS_SDRAM1 0x20000080 /* address of the SDRAM */
118 #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to SDRAM */
119 #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
120 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
121 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
122 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
123 #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
126 * Command line configuration
129 #include <config_cmd_default.h>
131 #define CONFIG_CMD_BMP
132 #define CONFIG_CMD_DATE
133 #define CONFIG_CMD_DHCP
134 #define CONFIG_CMD_I2C
135 #define CONFIG_CMD_JFFS2
136 #define CONFIG_CMD_MII
137 #define CONFIG_CMD_NAND
138 #define CONFIG_CMD_PING
139 #define CONFIG_I2C_CMD_NO_FLAT
140 #define CONFIG_I2C_CMD_TREE
142 #define CONFIG_SYS_LONGHELP
148 #define CONFIG_JFFS2_NAND 1
150 #ifndef CONFIG_JFFS2_CMDLINE
151 #define CONFIG_JFFS2_DEV "nand0"
152 #define CONFIG_JFFS2_PART_OFFSET 0
153 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
155 #define MTDIDS_DEFAULT "nor0=0,nand0=1"
156 #define MTDPARTS_DEFAULT "mtdparts=" \
166 #endif /* CONFIG_JFFS2_CMDLINE */
176 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
178 #define CONFIG_BAUDRATE 115200
179 #define CONFIG_AT91RM9200_USART
180 #define CONFIG_DBGU /* define DBGU as console */
185 #define CONFIG_NET_MULTI 1
187 #define CONFIG_NET_RETRY_COUNT 10
188 #define CONFIG_RESET_PHY_R 1
190 #define CONFIG_DRIVER_AT91EMAC 1
191 #define CONFIG_DRIVER_AT91EMAC_QUIET 1
192 #define CONFIG_SYS_RX_ETH_BUFFER 8
198 #define CONFIG_BOOTP_BOOTFILESIZE
199 #define CONFIG_BOOTP_BOOTPATH
200 #define CONFIG_BOOTP_GATEWAY
201 #define CONFIG_BOOTP_HOSTNAME
207 #define CONFIG_SYS_I2C_SPEED 50000
208 #define CONFIG_SYS_I2C_SLAVE 0 /* not used */
210 #ifndef CONFIG_HARD_I2C
211 #define CONFIG_SOFT_I2C
213 /* Software I2C driver configuration */
215 #define AT91_PIN_SDA (1<<25) /* AT91C_PIO_PA25 */
216 #define AT91_PIN_SCL (1<<26) /* AT91C_PIO_PA26 */
218 #define CONFIG_SYS_I2C_INIT_BOARD
220 #define I2C_INIT i2c_init_board();
221 #define I2C_ACTIVE writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
222 #define I2C_TRISTATE writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
223 #define I2C_READ ((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
224 #define I2C_SDA(bit) \
226 writel(AT91_PMX_AA_TWD, &pio->pioa.sodr); \
228 writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
229 #define I2C_SCL(bit) \
231 writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr); \
233 writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
235 #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
237 #endif /* CONFIG_HARD_I2C */
241 #ifdef CONFIG_CMD_DATE
242 #define CONFIG_RTC_DS1338
243 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
248 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
249 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
251 /* FLASH organization */
254 #define CONFIG_FLASH_SHOW_PROGRESS 45
256 #define CONFIG_FLASH_CFI_DRIVER 1
258 #define PHYS_FLASH_1 0x10000000
259 #define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main flash */
260 #define CONFIG_SYS_FLASH_CFI 1
261 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
263 #define CONFIG_SYS_FLASH_PROTECTION 1
264 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
265 #define CONFIG_SYS_MAX_FLASH_BANKS 1
266 #define CONFIG_SYS_MAX_FLASH_SECT 512
267 #define CONFIG_SYS_FLASH_ERASE_TOUT 6000
268 #define CONFIG_SYS_FLASH_WRITE_TOUT 2000
272 #define CONFIG_SYS_NAND_MAX_CHIPS 1
273 #define CONFIG_SYS_MAX_NAND_DEVICE 1
274 #define CONFIG_SYS_NAND_BASE 0x40000000
275 #define CONFIG_SYS_NAND_DBW_8 1
277 #define CONFIG_SYS_64BIT_VSPRINTF 1
281 #define CONFIG_STATUS_LED 1
282 #define CONFIG_BOARD_SPECIFIC_LED 1
284 #define STATUS_LED_BOOT 1
285 #define STATUS_LED_ACTIVE 0
287 #define STATUS_LED_BIT 1 /* AT91C_PIO_PD0 green LED */
288 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
289 #define STATUS_LED_STATE STATUS_LED_OFF /* BLINKING */
290 #define STATUS_LED_BIT1 2 /* AT91C_PIO_PD1 red LED */
291 #define STATUS_LED_STATE1 STATUS_LED_ON /* BLINKING */
292 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 4)
294 #define CONFIG_VIDEO 1
300 #define CONFIG_VIDEO_VCXK 1
302 #define CONFIG_SPLASH_SCREEN 1
304 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 4
305 #define CONFIG_SYS_VCXK_BASE 0x30000000
307 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN (1<<3)
308 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT piob
309 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR odr
311 #define CONFIG_SYS_VCXK_ENABLE_PIN (1<<5)
312 #define CONFIG_SYS_VCXK_ENABLE_PORT piob
313 #define CONFIG_SYS_VCXK_ENABLE_DDR oer
315 #define CONFIG_SYS_VCXK_REQUEST_PIN (1<<2)
316 #define CONFIG_SYS_VCXK_REQUEST_PORT piob
317 #define CONFIG_SYS_VCXK_REQUEST_DDR oer
319 #define CONFIG_SYS_VCXK_INVERT_PIN (1<<4)
320 #define CONFIG_SYS_VCXK_INVERT_PORT piob
321 #define CONFIG_SYS_VCXK_INVERT_DDR oer
323 #define CONFIG_SYS_VCXK_RESET_PIN (1<<6)
324 #define CONFIG_SYS_VCXK_RESET_PORT piob
325 #define CONFIG_SYS_VCXK_RESET_DDR oer
327 #endif /* CONFIG_VIDEO */
331 #define CONFIG_BOOTDELAY 5
333 #define CONFIG_ENV_IS_IN_FLASH 1
334 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
335 #define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */
337 #define CONFIG_BAUDRATE 115200
339 #define CONFIG_BOOTCOMMAND "run nfsboot"
341 #define CONFIG_NFSBOOTCOMMAND \
342 "dhcp $(copy_addr) uImage_cpux9k2;" \
343 "run bootargsdefaults;" \
344 "set bootargs $(bootargs) boot=nfs " \
345 ";echo $(bootargs)" \
348 #define CONFIG_EXTRA_ENV_SETTINGS \
349 "displaywidth=256\0" \
350 "displayheight=512\0" \
351 "displaybsteps=1023\0" \
352 "ubootaddr=10000000\0" \
353 "splashimage=10080000\0" \
354 "kerneladdr=100A0000\0" \
355 "kernelsize=00400000\0" \
356 "rootfsaddr=104A0000\0" \
357 "copy_addr=21200000\0" \
358 "rootfssize=00B60000\0" \
359 "bootargsdefaults=set bootargs " \
360 "console=ttyS0,115200 " \
361 "video=vcxk_fb:xres:${displaywidth}," \
362 "yres:${displayheight}," \
363 "bres:${displaybsteps} " \
366 "uboot=\\\"${ver}\\\" " \
368 "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
369 "dhcp $(copy_addr) uImage_cpux9k2;" \
370 "erase $(kerneladdr) +$(kernelsize);" \
371 "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
372 "protect on $(kerneladdr) +$(kernelsize)" \
374 "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
375 "dhcp $(copy_addr) rfs;" \
376 "erase $(rootfsaddr) +$(rootfssize);" \
377 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
379 "update_uboot=protect off 10000000 1005FFFF;" \
380 "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \
381 "erase 10000000 1005FFFF;" \
382 "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
383 "protect on 10000000 1005FFFF;reset\0" \
384 "update_splash=protect off $(splashimage) +20000;" \
385 "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \
386 "erase $(splashimage) +20000;" \
387 "cp.b $(fileaddr) 10080000 $(filesize);" \
388 "protect on $(splashimage) +20000;reset\0" \
389 "emergency=run bootargsdefaults;" \
390 "set bootargs $(bootargs) root=initramfs boot=emergency " \
391 ";bootm $(kerneladdr)\0" \
392 "netemergency=run bootargsdefaults;" \
393 "dhcp $(copy_addr) uImage_cpux9k2;" \
394 "set bootargs $(bootargs) root=initramfs boot=emergency " \
395 ";bootm $(copy_addr)\0" \
396 "norboot=run bootargsdefaults;" \
397 "set bootargs $(bootargs) root=initramfs boot=local " \
398 ";bootm $(kerneladdr)\0" \
399 "nandboot=run bootargsdefaults;" \
400 "set bootargs $(bootargs) root=initramfs boot=nand " \
401 ";bootm $(kerneladdr)\0" \
404 /*--------------------------------------------------------------------------*/