2 * Copyright (C) 2012 Samsung Electronics
4 * Configuration settings for the SAMSUNG EXYNOS5250 board.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* High Level Configuration Options */
29 #define CONFIG_SAMSUNG /* in a SAMSUNG core */
30 #define CONFIG_S5P /* S5P Family */
31 #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
32 #define CONFIG_SMDK5250 /* which is in a SMDK5250 */
34 #include <asm/arch/cpu.h> /* get chip and board defs */
36 #define CONFIG_SYS_GENERIC_BOARD
37 #define CONFIG_ARCH_CPU_INIT
38 #define CONFIG_DISPLAY_CPUINFO
39 #define CONFIG_DISPLAY_BOARDINFO
41 /* Enable fdt support for Exynos5250 */
42 #define CONFIG_ARCH_DEVICE_TREE exynos5250
43 #define CONFIG_OF_CONTROL
44 #define CONFIG_OF_SEPARATE
46 /* Keep L2 Cache Disabled */
47 #define CONFIG_SYS_DCACHE_OFF
49 /* Enable ACE acceleration for SHA1 and SHA256 */
50 #define CONFIG_EXYNOS_ACE_SHA
51 #define CONFIG_SHA_HW_ACCEL
53 #define CONFIG_SYS_SDRAM_BASE 0x40000000
54 #define CONFIG_SYS_TEXT_BASE 0x43E00000
56 /* input clock of PLL: SMDK5250 has 24MHz input clock */
57 #define CONFIG_SYS_CLK_FREQ 24000000
59 #define CONFIG_SETUP_MEMORY_TAGS
60 #define CONFIG_CMDLINE_TAG
61 #define CONFIG_INITRD_TAG
62 #define CONFIG_CMDLINE_EDITING
64 /* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
65 #define MACH_TYPE_SMDK5250 3774
66 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
68 /* Power Down Modes */
69 #define S5P_CHECK_SLEEP 0x00000BAD
70 #define S5P_CHECK_DIDLE 0xBAD00000
71 #define S5P_CHECK_LPA 0xABAD0000
73 /* Offset for inform registers */
74 #define INFORM0_OFFSET 0x800
75 #define INFORM1_OFFSET 0x804
77 /* Size of malloc() pool */
78 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
80 /* select serial console configuration */
81 #define CONFIG_SERIAL3 /* use SERIAL 3 */
82 #define CONFIG_BAUDRATE 115200
83 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
85 /* Console configuration */
86 #define CONFIG_CONSOLE_MUX
87 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
88 #define EXYNOS_DEVICE_SETTINGS \
90 "stdout=serial,lcd\0" \
93 #define CONFIG_EXTRA_ENV_SETTINGS \
94 EXYNOS_DEVICE_SETTINGS
96 #define TZPC_BASE_OFFSET 0x10000
98 /* SD/MMC configuration */
99 #define CONFIG_GENERIC_MMC
102 #define CONFIG_S5P_SDHCI
104 #define CONFIG_BOARD_EARLY_INIT_F
109 /* allow to overwrite serial and ethaddr */
110 #define CONFIG_ENV_OVERWRITE
112 /* Command definition*/
113 #include <config_cmd_default.h>
115 #define CONFIG_CMD_PING
116 #define CONFIG_CMD_ELF
117 #define CONFIG_CMD_MMC
118 #define CONFIG_CMD_EXT2
119 #define CONFIG_CMD_FAT
120 #define CONFIG_CMD_NET
121 #define CONFIG_CMD_HASH
123 #define CONFIG_BOOTDELAY 3
124 #define CONFIG_ZERO_BOOTDELAY_CHECK
126 /* Thermal Management Unit */
127 #define CONFIG_EXYNOS_TMU
128 #define CONFIG_CMD_DTT
129 #define CONFIG_TMU_CMD_DTT
132 #define CONFIG_CMD_USB
133 #define CONFIG_USB_EHCI
134 #define CONFIG_USB_EHCI_EXYNOS
135 #define CONFIG_USB_STORAGE
138 #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
139 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
140 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
144 #define COPY_BL2_FNPTR_ADDR 0x02020030
146 /* specific .lds file */
147 #define CONFIG_SPL_LDSCRIPT "board/samsung/smdk5250/smdk5250-uboot-spl.lds"
148 #define CONFIG_SPL_TEXT_BASE 0x02023400
149 #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
151 #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
153 /* Miscellaneous configurable options */
154 #define CONFIG_SYS_LONGHELP /* undef to save memory */
155 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
156 #define CONFIG_SYS_PROMPT "SMDK5250 # "
157 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
158 #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
159 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
160 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
161 /* Boot Argument Buffer Size */
162 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
163 /* memtest works on */
164 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
165 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
166 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
168 #define CONFIG_SYS_HZ 1000
170 #define CONFIG_RD_LVL
172 #define CONFIG_NR_DRAM_BANKS 8
173 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
174 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
175 #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
176 #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
177 #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
178 #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
179 #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
180 #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
181 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
182 #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
183 #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
184 #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
185 #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
186 #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
187 #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
188 #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
189 #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
191 #define CONFIG_SYS_MONITOR_BASE 0x00000000
193 /* FLASH and environment organization */
194 #define CONFIG_SYS_NO_FLASH
195 #undef CONFIG_CMD_IMLS
196 #define CONFIG_IDENT_STRING " for SMDK5250"
198 #define CONFIG_SYS_MMC_ENV_DEV 0
200 #define CONFIG_SECURE_BL1_ONLY
202 /* Secure FW size configuration */
203 #ifdef CONFIG_SECURE_BL1_ONLY
204 #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
206 #define CONFIG_SEC_FW_SIZE 0
209 /* Configuration of BL1, BL2, ENV Blocks on mmc */
210 #define CONFIG_RES_BLOCK_SIZE (512)
211 #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
212 #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
213 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
215 #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
216 #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
217 #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
219 /* U-boot copy size from boot Media to DRAM.*/
220 #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
221 #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
223 #define OM_STAT (0x1f << 1)
224 #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
225 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
227 #define CONFIG_DOS_PARTITION
229 #define CONFIG_IRAM_STACK 0x02050000
231 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
234 #define CONFIG_SYS_I2C_INIT_BOARD
235 #define CONFIG_HARD_I2C
236 #define CONFIG_CMD_I2C
237 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
238 #define CONFIG_DRIVER_S3C24X0_I2C
239 #define CONFIG_I2C_MULTI_BUS
240 #define CONFIG_MAX_I2C_NUM 8
241 #define CONFIG_SYS_I2C_SLAVE 0x0
242 #define CONFIG_I2C_EDID
246 #define CONFIG_PMIC_I2C
247 #define CONFIG_PMIC_MAX77686
250 #define CONFIG_ENV_IS_IN_SPI_FLASH
251 #define CONFIG_SPI_FLASH
253 #ifdef CONFIG_SPI_FLASH
254 #define CONFIG_EXYNOS_SPI
255 #define CONFIG_CMD_SF
256 #define CONFIG_CMD_SPI
257 #define CONFIG_SPI_FLASH_WINBOND
258 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
259 #define CONFIG_SF_DEFAULT_SPEED 50000000
260 #define EXYNOS5_SPI_NUM_CONTROLLERS 5
263 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
264 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
265 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
266 #define CONFIG_ENV_SPI_BUS 1
267 #define CONFIG_ENV_SPI_MAX_HZ 50000000
272 #define CONFIG_POWER_I2C
273 #define CONFIG_POWER_MAX77686
276 #define CONFIG_ENV_IS_IN_SPI_FLASH
277 #define CONFIG_SPI_FLASH
279 #ifdef CONFIG_SPI_FLASH
280 #define CONFIG_EXYNOS_SPI
281 #define CONFIG_CMD_SF
282 #define CONFIG_CMD_SPI
283 #define CONFIG_SPI_FLASH_WINBOND
284 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
285 #define CONFIG_SF_DEFAULT_SPEED 50000000
286 #define EXYNOS5_SPI_NUM_CONTROLLERS 5
289 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
290 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
291 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
292 #define CONFIG_ENV_SPI_BUS 1
293 #define CONFIG_ENV_SPI_MAX_HZ 50000000
296 /* Ethernet Controllor Driver */
297 #ifdef CONFIG_CMD_NET
298 #define CONFIG_SMC911X
299 #define CONFIG_SMC911X_BASE 0x5000000
300 #define CONFIG_SMC911X_16_BIT
301 #define CONFIG_ENV_SROM_BANK 1
302 #endif /*CONFIG_CMD_NET*/
304 /* Enable PXE Support */
305 #ifdef CONFIG_CMD_NET
306 #define CONFIG_CMD_PXE
311 #define CONFIG_CMD_SOUND
312 #ifdef CONFIG_CMD_SOUND
315 #define CONFIG_SOUND_MAX98095
316 #define CONFIG_SOUND_WM8994
319 /* Enable devicetree support */
320 #define CONFIG_OF_LIBFDT
323 #define CONFIG_CMD_HASH
324 #define CONFIG_HASH_VERIFY
326 #define CONFIG_SHA256
331 #define CONFIG_EXYNOS_FB
332 #define CONFIG_EXYNOS_DP
333 #define LCD_XRES 2560
334 #define LCD_YRES 1600
335 #define LCD_BPP LCD_COLOR16
338 /* Enable Time Command */
339 #define CONFIG_CMD_TIME
341 #endif /* __CONFIG_H */