git.sur5r.net Git - u-boot/blob - include/configs/h2200.h

   1 /*
   2  * iPAQ h2200 board configuration
   3  *
   4  * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define MACH_TYPE_H2200                 341
  13 #define CONFIG_MACH_TYPE                MACH_TYPE_H2200
  14
  15 #define CONFIG_CPU_PXA25X               1
  16 #define CONFIG_BOARD_H2200
  17
  18 #define CONFIG_SYS_NO_FLASH
  19
  20 #define CONFIG_NR_DRAM_BANKS            1
  21 #define PHYS_SDRAM_1                    0xa0000000 /* SDRAM Bank #1 */
  22 #define PHYS_SDRAM_1_SIZE               0x04000000 /* 64 MB */
  23
  24 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  25 #define CONFIG_SYS_SDRAM_SIZE           PHYS_SDRAM_1_SIZE
  26
  27 #define CONFIG_SYS_INIT_SP_ADDR         0xfffff800
  28
  29 #define CONFIG_ENV_SIZE                 0x00040000
  30 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128*1024)
  31
  32 #define CONFIG_ENV_IS_NOWHERE
  33 #define CONFIG_SYS_MAXARGS              16
  34 #define CONFIG_SYS_LOAD_ADDR            0xa3000000 /* default load address */
  35
  36 /*
  37  * iPAQ 1st stage bootloader loads 2nd stage bootloader
  38  * at address 0xa0040000 but bootloader requires header
  39  * which is 0x1000 long.
  40  *
  41  * --- Header begin ---
  42  *      .word 0xea0003fe ; b 0x1000
  43  *
  44  *      .org 0x40
  45  *      .ascii "ECEC"
  46  *
  47  *      .org 0x1000
  48  * --- Header end ---
  49  */
  50
  51 #define CONFIG_SYS_TEXT_BASE            0xa0041000
  52
  53 /*
  54  * Static chips
  55  */
  56
  57 #define CONFIG_SYS_MSC0_VAL             0x246c7ffc
  58 #define CONFIG_SYS_MSC1_VAL             0x7ff07ff0
  59 #define CONFIG_SYS_MSC2_VAL             0x7ff07ff0
  60
  61 /*
  62  * PCMCIA and CF Interfaces
  63  */
  64
  65 #define CONFIG_SYS_MECR_VAL             0x00000000
  66 #define CONFIG_SYS_MCMEM0_VAL           0x00000000
  67 #define CONFIG_SYS_MCMEM1_VAL           0x00000000
  68 #define CONFIG_SYS_MCATT0_VAL           0x00000000
  69 #define CONFIG_SYS_MCATT1_VAL           0x00000000
  70 #define CONFIG_SYS_MCIO0_VAL            0x00000000
  71 #define CONFIG_SYS_MCIO1_VAL            0x00000000
  72
  73 #define CONFIG_SYS_FLYCNFG_VAL          0x00000000
  74 #define CONFIG_SYS_SXCNFG_VAL           0x00040004
  75
  76 #define CONFIG_SYS_MDREFR_VAL           0x0099E018
  77 #define CONFIG_SYS_MDCNFG_VAL           0x01C801CB
  78 #define CONFIG_SYS_MDMRS_VAL            0x00220022
  79
  80 #define CONFIG_SYS_PSSR_VAL             0x00000000
  81 #define CONFIG_SYS_CKEN                 0x00004840
  82 #define CONFIG_SYS_CCCR                 0x00000161
  83
  84 /*
  85  * GPIOs
  86  */
  87
  88 #define CONFIG_SYS_GPSR0_VAL            0x01000000
  89 #define CONFIG_SYS_GPSR1_VAL            0x00000000
  90 #define CONFIG_SYS_GPSR2_VAL            0x00010000
  91
  92 #define CONFIG_SYS_GPCR0_VAL            0x00000000
  93 #define CONFIG_SYS_GPCR1_VAL            0x00000000
  94 #define CONFIG_SYS_GPCR2_VAL            0x00000000
  95
  96 #define CONFIG_SYS_GPDR0_VAL            0xF7E38C00
  97 #define CONFIG_SYS_GPDR1_VAL            0xBCFFBF83
  98 #define CONFIG_SYS_GPDR2_VAL            0x000157FF
  99
 100 #define CONFIG_SYS_GAFR0_L_VAL          0x80401000
 101 #define CONFIG_SYS_GAFR0_U_VAL          0x00000112
 102 #define CONFIG_SYS_GAFR1_L_VAL          0x600A9550
 103 #define CONFIG_SYS_GAFR1_U_VAL          0x0005AAAA
 104 #define CONFIG_SYS_GAFR2_L_VAL          0x20000000
 105 #define CONFIG_SYS_GAFR2_U_VAL          0x00000000
 106
 107 /*
 108  * Serial port
 109  */
 110
 111 #define CONFIG_PXA_SERIAL
 112 #define CONFIG_FFUART
 113 #define CONFIG_CONS_INDEX               3
 114
 115 #define CONFIG_BAUDRATE                 115200
 116 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 38400, 115200 }
 117
 118 #define CONFIG_FIT
 119 #define CONFIG_FIT_DISABLE_SHA256
 120 #define CONFIG_SETUP_MEMORY_TAGS
 121 #define CONFIG_CMDLINE_TAG
 122 #define CONFIG_INITRD_TAG
 123
 124 /* Monitor Command Prompt */
 125 #define CONFIG_SYS_HUSH_PARSER
 126 #define CONFIG_SYS_PROMPT_HUSH_PS2      "$ "
 127
 128 /* Console I/O Buffer Size */
 129 #define CONFIG_SYS_CBSIZE               256
 130
 131 /* Print Buffer Size */
 132 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 133                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 134
 135 #define CONFIG_BOOTARGS "root=/dev/ram0 ro console=ttyS0,115200n8"
 136
 137 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 138 #define CONFIG_USB_DEV_PULLUP_GPIO      33
 139 /* USB VBUS GPIO 3 */
 140
 141 #define CONFIG_CMD_PING
 142
 143 #define CONFIG_BOOTDELAY                2
 144 #define CONFIG_BOOTCOMMAND              \
 145         "setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \
 146         "if bootp ; then setenv downloaded 1 ; fi ; done ; " \
 147         "source :script ; " \
 148         "bootm ; "
 149
 150 #define CONFIG_USB_GADGET_PXA2XX
 151 #define CONFIG_USB_ETHER
 152 #define CONFIG_USB_ETH_SUBSET
 153
 154 #define CONFIG_USBNET_DEV_ADDR          "de:ad:be:ef:00:01"
 155 #define CONFIG_USBNET_HOST_ADDR "de:ad:be:ef:00:02"
 156 #define CONFIG_EXTRA_ENV_SETTINGS \
 157         "stdin=serial\0" \
 158         "stdout=serial\0" \
 159         "stderr=serial\0"
 160
 161 #endif /* __CONFIG_H */