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1 /*
2  * (C) Copyright 2013
3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4  *
5  * Based on:
6  * Copyright (c) 2011 IDS GmbH, Germany
7  * Sergej Stepanov <ste@ids.de>
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14
15 /*
16  * High Level Configuration Options
17  */
18 #define CONFIG_MPC831x
19 #define CONFIG_MPC8313
20 #define CONFIG_IDS8313
21
22 #define CONFIG_FSL_ELBC
23
24 #define CONFIG_MISC_INIT_R
25
26 #define CONFIG_BOOT_RETRY_TIME          900
27 #define CONFIG_BOOT_RETRY_MIN           30
28 #define CONFIG_RESET_TO_RETRY
29
30 #define CONFIG_83XX_CLKIN               66000000        /* in Hz */
31 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
32
33 #define CONFIG_SYS_IMMR         0xF0000000
34
35 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
36 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
37
38 /*
39  * Hardware Reset Configuration Word
40  * if CLKIN is 66.000MHz, then
41  * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
42  */
43 #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
44                              HRCWL_DDR_TO_SCB_CLK_2X1 |\
45                              HRCWL_CSB_TO_CLKIN_2X1 |\
46                              HRCWL_CORE_TO_CSB_2X1)
47
48 #define CONFIG_SYS_HRCW_HIGH    (HRCWH_PCI_HOST |\
49                                  HRCWH_CORE_ENABLE |\
50                                  HRCWH_FROM_0XFFF00100 |\
51                                  HRCWH_BOOTSEQ_DISABLE |\
52                                  HRCWH_SW_WATCHDOG_DISABLE |\
53                                  HRCWH_ROM_LOC_LOCAL_8BIT |\
54                                  HRCWH_RL_EXT_LEGACY |\
55                                  HRCWH_TSEC1M_IN_MII |\
56                                  HRCWH_TSEC2M_IN_MII |\
57                                  HRCWH_BIG_ENDIAN)
58
59 #define CONFIG_SYS_SICRH        0x00000000
60 #define CONFIG_SYS_SICRL        (SICRL_LBC | SICRL_SPI_D)
61
62 #define CONFIG_HWCONFIG
63
64 #define CONFIG_SYS_HID0_INIT    0x000000000
65 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK |\
66                                  HID0_ENABLE_INSTRUCTION_CACHE |\
67                                  HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
68
69 #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
70
71 /*
72  * Definitions for initial stack pointer and data area (in DCACHE )
73  */
74 #define CONFIG_SYS_INIT_RAM_LOCK
75 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
76 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* End of used area in DPRAM */
77 #define CONFIG_SYS_GBL_DATA_SIZE        0x100
78 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
79                                          - CONFIG_SYS_GBL_DATA_SIZE)
80 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
81
82 /*
83  * Local Bus LCRR and LBCR regs
84  */
85 #define CONFIG_SYS_LCRR_EADC            LCRR_EADC_1
86 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
87 #define CONFIG_SYS_LBC_LBCR             (0x00040000 |\
88                                          (0xFF << LBCR_BMT_SHIFT) |\
89                                          0xF)
90
91 #define CONFIG_SYS_LBC_MRTPR            0x20000000
92
93 /*
94  * Internal Definitions
95  */
96 /*
97  * DDR Setup
98  */
99 #define CONFIG_SYS_DDR_BASE             0x00000000
100 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
101 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
102
103 /*
104  * Manually set up DDR parameters,
105  * as this board has not the SPD connected to I2C.
106  */
107 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
108 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN |\
109                                          0x00010000 |\
110                                          CSCONFIG_ROW_BIT_13 |\
111                                          CSCONFIG_COL_BIT_10)
112
113 #define CONFIG_SYS_DDR_CONFIG_256       (CONFIG_SYS_DDR_CONFIG | \
114                                          CSCONFIG_BANK_BIT_3)
115
116 #define CONFIG_SYS_DDR_TIMING_3 (1 << 16)       /* ext refrec */
117 #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
118                                 (3 << TIMING_CFG0_WRT_SHIFT) |\
119                                 (3 << TIMING_CFG0_RRT_SHIFT) |\
120                                 (3 << TIMING_CFG0_WWT_SHIFT) |\
121                                 (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
122                                 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
123                                 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
124                                 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
125 #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
126                                 (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
127                                 (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
128                                 (7 << TIMING_CFG1_CASLAT_SHIFT) |\
129                                 (4 << TIMING_CFG1_REFREC_SHIFT) |\
130                                 (4 << TIMING_CFG1_WRREC_SHIFT) |\
131                                 (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
132                                 (2 << TIMING_CFG1_WRTORD_SHIFT))
133 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
134                                 (5 << TIMING_CFG2_CPO_SHIFT) |\
135                                 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
136                                 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
137                                 (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
138                                 (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
139                                 (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
140
141 #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
142                                 (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
143
144 #define CONFIG_SYS_SDRAM_CFG            (SDRAM_CFG_SREN |\
145                                          SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
146                                          SDRAM_CFG_DBW_32 |\
147                                          SDRAM_CFG_SDRAM_TYPE_DDR2)
148
149 #define CONFIG_SYS_SDRAM_CFG2           0x00401000
150 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
151                                          (0x0242 << SDRAM_MODE_SD_SHIFT))
152 #define CONFIG_SYS_DDR_MODE_2           0x00000000
153 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
154 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
155                                          DDRCDR_PZ_NOMZ |\
156                                          DDRCDR_NZ_NOMZ |\
157                                          DDRCDR_ODT |\
158                                          DDRCDR_M_ODR |\
159                                          DDRCDR_Q_DRN)
160
161 /*
162  * on-board devices
163  */
164 #define CONFIG_TSEC1
165 #define CONFIG_TSEC2
166 #define CONFIG_TSEC_ENET
167 #define CONFIG_HARD_SPI
168
169 /*
170  * NOR FLASH setup
171  */
172 #define CONFIG_SYS_FLASH_CFI
173 #define CONFIG_FLASH_CFI_DRIVER
174 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
175 #define CONFIG_FLASH_SHOW_PROGRESS      50
176 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
177
178 #define CONFIG_SYS_FLASH_BASE           0xFF800000
179 #define CONFIG_SYS_FLASH_SIZE           8
180 #define CONFIG_SYS_FLASH_PROTECTION
181
182 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
183 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016
184
185 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |\
186                                          BR_PS_8 |\
187                                          BR_MS_GPCM |\
188                                          BR_V)
189
190 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
191                                          OR_GPCM_SCY_10 |\
192                                          OR_GPCM_EHTR |\
193                                          OR_GPCM_TRLX |\
194                                          OR_GPCM_CSNT |\
195                                          OR_GPCM_EAD)
196 #define CONFIG_SYS_MAX_FLASH_BANKS      1
197 #define CONFIG_SYS_MAX_FLASH_SECT       128
198
199 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000
200 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
201
202 /*
203  * NAND FLASH setup
204  */
205 #define CONFIG_SYS_NAND_BASE            0xE1000000
206 #define CONFIG_SYS_MAX_NAND_DEVICE      1
207 #define CONFIG_SYS_NAND_MAX_CHIPS       1
208 #define CONFIG_NAND_FSL_ELBC
209 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)
210 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)
211 #define NAND_CACHE_PAGES                64
212
213 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
214 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E
215 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
216 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR1_PRELIM
217
218 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_NAND_BASE) |\
219                                  (2<<BR_DECC_SHIFT) |\
220                                  BR_PS_8 |\
221                                  BR_MS_FCM |\
222                                  BR_V)
223
224 #define CONFIG_SYS_OR1_PRELIM   (0xFFFF8000 |\
225                                  OR_FCM_PGS |\
226                                  OR_FCM_CSCT |\
227                                  OR_FCM_CST |\
228                                  OR_FCM_CHT |\
229                                  OR_FCM_SCY_4 |\
230                                  OR_FCM_TRLX |\
231                                  OR_FCM_EHTR |\
232                                  OR_FCM_RST)
233
234 /*
235  * MRAM setup
236  */
237 #define CONFIG_SYS_MRAM_BASE            0xE2000000
238 #define CONFIG_SYS_MRAM_SIZE            0x20000 /* 128 Kb */
239 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_MRAM_BASE
240 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000010      /* 128 Kb  */
241
242 #define CONFIG_SYS_OR_TIMING_MRAM
243
244 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_MRAM_BASE |\
245                                          BR_PS_8 |\
246                                          BR_MS_GPCM |\
247                                          BR_V)
248
249 #define CONFIG_SYS_OR2_PRELIM           0xFFFE0C74
250
251 /*
252  * CPLD setup
253  */
254 #define CONFIG_SYS_CPLD_BASE            0xE3000000
255 #define CONFIG_SYS_CPLD_SIZE            0x8000
256 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CPLD_BASE
257 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E
258
259 #define CONFIG_SYS_OR_TIMING_MRAM
260
261 #define CONFIG_SYS_BR3_PRELIM           (CONFIG_SYS_CPLD_BASE |\
262                                          BR_PS_8 |\
263                                          BR_MS_GPCM |\
264                                          BR_V)
265
266 #define CONFIG_SYS_OR3_PRELIM           0xFFFF8814
267
268 /*
269  * HW-Watchdog
270  */
271 #define CONFIG_WATCHDOG         1
272 #define CONFIG_SYS_WATCHDOG_VALUE       0xFFFF
273
274 /*
275  * I2C setup
276  */
277 #define CONFIG_SYS_I2C
278 #define CONFIG_SYS_I2C_FSL
279 #define CONFIG_SYS_FSL_I2C_SPEED        400000
280 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
281 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
282 #define CONFIG_RTC_PCF8563
283 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
284
285 /*
286  * SPI setup
287  */
288 #ifdef CONFIG_HARD_SPI
289 #define CONFIG_MPC8XXX_SPI
290 #define CONFIG_SYS_GPIO1_PRELIM
291 #define CONFIG_SYS_GPIO1_DIR            0x00000001
292 #define CONFIG_SYS_GPIO1_DAT            0x00000001
293 #endif
294
295 /*
296  * Ethernet setup
297  */
298 #ifdef CONFIG_TSEC1
299 #define CONFIG_HAS_ETH0
300 #define CONFIG_TSEC1_NAME               "TSEC0"
301 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
302 #define TSEC1_PHY_ADDR                  0x1
303 #define TSEC1_FLAGS                     TSEC_GIGABIT
304 #define TSEC1_PHYIDX                    0
305 #endif
306
307 #ifdef CONFIG_TSEC2
308 #define CONFIG_HAS_ETH1
309 #define CONFIG_TSEC2_NAME               "TSEC1"
310 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
311 #define TSEC2_PHY_ADDR                  0x3
312 #define TSEC2_FLAGS                     TSEC_GIGABIT
313 #define TSEC2_PHYIDX                    0
314 #endif
315 #define CONFIG_ETHPRIME         "TSEC1"
316
317 /*
318  * Serial Port
319  */
320 #define CONFIG_CONS_INDEX               1
321 #define CONFIG_SYS_NS16550_SERIAL
322 #define CONFIG_SYS_NS16550_REG_SIZE     1
323
324 #define CONFIG_SYS_BAUDRATE_TABLE       \
325         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
326 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
327 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
328 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
329
330 #define CONFIG_HAS_FSL_DR_USB
331 #define CONFIG_SYS_SCCR_USBDRCM 3
332
333 /*
334  * BAT's
335  */
336 #define CONFIG_HIGH_BATS
337
338 /* DDR @ 0x00000000 */
339 #define CONFIG_SYS_IBAT0L               (CONFIG_SYS_SDRAM_BASE |\
340                                          BATL_PP_10)
341 #define CONFIG_SYS_IBAT0U               (CONFIG_SYS_SDRAM_BASE |\
342                                          BATU_BL_256M |\
343                                          BATU_VS |\
344                                          BATU_VP)
345 #define CONFIG_SYS_DBAT0L               CONFIG_SYS_IBAT0L
346 #define CONFIG_SYS_DBAT0U               CONFIG_SYS_IBAT0U
347
348 /* Initial RAM @ 0xFD000000 */
349 #define CONFIG_SYS_IBAT1L               (CONFIG_SYS_INIT_RAM_ADDR |\
350                                          BATL_PP_10 |\
351                                          BATL_GUARDEDSTORAGE)
352 #define CONFIG_SYS_IBAT1U               (CONFIG_SYS_INIT_RAM_ADDR |\
353                                          BATU_BL_256K |\
354                                          BATU_VS |\
355                                          BATU_VP)
356 #define CONFIG_SYS_DBAT1L               CONFIG_SYS_IBAT1L
357 #define CONFIG_SYS_DBAT1U               CONFIG_SYS_IBAT1U
358
359 /* FLASH @ 0xFF800000 */
360 #define CONFIG_SYS_IBAT2L               (CONFIG_SYS_FLASH_BASE |\
361                                          BATL_PP_10 |\
362                                          BATL_GUARDEDSTORAGE)
363 #define CONFIG_SYS_IBAT2U               (CONFIG_SYS_FLASH_BASE |\
364                                          BATU_BL_8M |\
365                                          BATU_VS |\
366                                          BATU_VP)
367 #define CONFIG_SYS_DBAT2L               (CONFIG_SYS_FLASH_BASE |\
368                                          BATL_PP_10 |\
369                                          BATL_CACHEINHIBIT |\
370                                          BATL_GUARDEDSTORAGE)
371 #define CONFIG_SYS_DBAT2U               CONFIG_SYS_IBAT2U
372
373 #define CONFIG_SYS_IBAT3L               (0)
374 #define CONFIG_SYS_IBAT3U               (0)
375 #define CONFIG_SYS_DBAT3L               CONFIG_SYS_IBAT3L
376 #define CONFIG_SYS_DBAT3U               CONFIG_SYS_IBAT3U
377
378 #define CONFIG_SYS_IBAT4L               (0)
379 #define CONFIG_SYS_IBAT4U               (0)
380 #define CONFIG_SYS_DBAT4L               CONFIG_SYS_IBAT4L
381 #define CONFIG_SYS_DBAT4U               CONFIG_SYS_IBAT4U
382
383 /* IMMRBAR @ 0xF0000000 */
384 #define CONFIG_SYS_IBAT5L               (CONFIG_SYS_IMMR |\
385                                          BATL_PP_10 |\
386                                          BATL_CACHEINHIBIT |\
387                                          BATL_GUARDEDSTORAGE)
388 #define CONFIG_SYS_IBAT5U               (CONFIG_SYS_IMMR |\
389                                          BATU_BL_128M |\
390                                          BATU_VS |\
391                                          BATU_VP)
392 #define CONFIG_SYS_DBAT5L               CONFIG_SYS_IBAT5L
393 #define CONFIG_SYS_DBAT5U               CONFIG_SYS_IBAT5U
394
395 /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
396 #define CONFIG_SYS_IBAT6L               (0xE0000000 |\
397                                          BATL_PP_10 |\
398                                          BATL_GUARDEDSTORAGE)
399 #define CONFIG_SYS_IBAT6U               (0xE0000000 |\
400                                          BATU_BL_256M |\
401                                          BATU_VS |\
402                                          BATU_VP)
403 #define CONFIG_SYS_DBAT6L               CONFIG_SYS_IBAT6L
404 #define CONFIG_SYS_DBAT6U               CONFIG_SYS_IBAT6U
405
406 #define CONFIG_SYS_IBAT7L               (0)
407 #define CONFIG_SYS_IBAT7U               (0)
408 #define CONFIG_SYS_DBAT7L               CONFIG_SYS_IBAT7L
409 #define CONFIG_SYS_DBAT7U               CONFIG_SYS_IBAT7U
410
411 /*
412  * U-Boot environment setup
413  */
414 #define CONFIG_CMD_NAND
415 #define CONFIG_CMDLINE_EDITING
416 #define CONFIG_BOOTP_SUBNETMASK
417 #define CONFIG_BOOTP_GATEWAY
418 #define CONFIG_BOOTP_HOSTNAME
419 #define CONFIG_BOOTP_BOOTPATH
420 #define CONFIG_BOOTP_BOOTFILESIZE
421
422 /*
423  * The reserved memory
424  */
425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
426 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
427 #define CONFIG_SYS_MALLOC_LEN           (8 * 1024 * 1024)
428
429 /*
430  * Environment Configuration
431  */
432 #define CONFIG_ENV_IS_IN_FLASH
433 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE \
434                                 + CONFIG_SYS_MONITOR_LEN)
435 #define CONFIG_ENV_SIZE         0x20000
436 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
437 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
438
439 #define CONFIG_NETDEV                   eth1
440 #define CONFIG_HOSTNAME         ids8313
441 #define CONFIG_ROOTPATH         "/opt/eldk-4.2/ppc_6xx"
442 #define CONFIG_BOOTFILE         "ids8313/uImage"
443 #define CONFIG_UBOOTPATH                "ids8313/u-boot.bin"
444 #define CONFIG_FDTFILE                  "ids8313/ids8313.dtb"
445 #define CONFIG_LOADADDR         0x400000
446 #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
447
448 /* Initial Memory map for Linux*/
449 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
450
451 /*
452  * Miscellaneous configurable options
453  */
454 #define CONFIG_SYS_LONGHELP
455 #define CONFIG_SYS_CBSIZE               1024
456 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE \
457                                          + sizeof(CONFIG_SYS_PROMPT)+16)
458 #define CONFIG_SYS_MAXARGS              16
459 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
460
461 #define CONFIG_SYS_MEMTEST_START        0x00001000
462 #define CONFIG_SYS_MEMTEST_END          0x00C00000
463
464 #define CONFIG_SYS_LOAD_ADDR            0x100000
465 #define CONFIG_MII
466 #define CONFIG_LOADS_ECHO
467 #define CONFIG_TIMESTAMP
468 #define CONFIG_PREBOOT                  "echo;" \
469                                         "echo Type \\\"run nfsboot\\\" " \
470                                         "to mount root filesystem over NFS;echo"
471 #undef  CONFIG_BOOTARGS
472 #define CONFIG_BOOTCOMMAND              "run boot_cramfs"
473 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
474
475 #define CONFIG_JFFS2_NAND
476 #define CONFIG_JFFS2_DEV                "0"
477
478 /* mtdparts command line support */
479 #define CONFIG_CMD_MTDPARTS
480 #define CONFIG_FLASH_CFI_MTD
481 #define CONFIG_MTD_DEVICE
482 #define MTDIDS_DEFAULT          "nor0=ff800000.flash,nand0=e1000000.flash"
483 #define MTDPARTS_DEFAULT        "mtdparts=ff800000.flash:7m(dum)," \
484                                         "768k(BOOT-BIN)," \
485                                         "128k(BOOT-ENV),128k(BOOT-REDENV);" \
486                                         "e1000000.flash:-(ubi)"
487
488 #define CONFIG_EXTRA_ENV_SETTINGS \
489         "netdev=" __stringify(CONFIG_NETDEV) "\0"                       \
490         "ethprime=TSEC1\0"                                              \
491         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
492         "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
493                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
494                 " +${filesize}; "                                       \
495                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
496                 " +${filesize}; "                                       \
497                 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)   \
498                 " ${filesize}; "                                        \
499                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
500                 " +${filesize}; "                                       \
501                 "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)  \
502                 " ${filesize}\0"                                        \
503         "console=ttyS0\0"                                               \
504         "fdtaddr=0x780000\0"                                            \
505         "kernel_addr=ff800000\0"                                        \
506         "fdtfile=" __stringify(CONFIG_FDTFILE) "\0"                     \
507         "setbootargs=setenv bootargs "                                  \
508                 "root=${rootdev} rw console=${console},"                \
509                         "${baudrate} ${othbootargs}\0"                  \
510         "setipargs=setenv bootargs root=${rootdev} rw "                 \
511                         "nfsroot=${serverip}:${rootpath} "              \
512                         "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
513                         "${netmask}:${hostname}:${netdev}:off "         \
514                         "console=${console},${baudrate} ${othbootargs}\0" \
515         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
516         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
517         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
518         "\0"
519
520 #define CONFIG_NFSBOOTCOMMAND                                           \
521         "setenv rootdev /dev/nfs;"                                      \
522         "run setipargs;run addmtd;"                                     \
523         "tftp ${loadaddr} ${bootfile};"                         \
524         "tftp ${fdtaddr} ${fdtfile};"                                   \
525         "fdt addr ${fdtaddr};"                                          \
526         "bootm ${loadaddr} - ${fdtaddr}"
527
528 /* UBI Support */
529 #define CONFIG_CMD_NAND_TRIMFFS
530 #define CONFIG_CMD_UBIFS
531 #define CONFIG_RBTREE
532 #define CONFIG_LZO
533 #define CONFIG_MTD_PARTITIONS
534
535 /* bootcount support */
536 #define CONFIG_BOOTCOUNT_LIMIT
537 #define CONFIG_BOOTCOUNT_I2C
538 #define CONFIG_BOOTCOUNT_ALEN   1
539 #define CONFIG_SYS_BOOTCOUNT_ADDR       0x9
540
541 #define CONFIG_IMAGE_FORMAT_LEGACY
542
543 #endif  /* __CONFIG_H */