2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34 #define CONFIG_INKA4X0 1 /* INKA4x0 board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
38 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39 #define BOOTFLAG_WARM 0x02 /* Software reboot */
41 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
43 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
44 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
45 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
49 * Serial console configuration
51 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
52 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
53 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
57 * 0x40000000 - 0x4fffffff - PCI Memory
58 * 0x50000000 - 0x50ffffff - PCI IO Space
61 #define CONFIG_PCI_PNP 1
62 #define CONFIG_PCI_SCAN_SHOW 1
64 #define CONFIG_PCI_MEM_BUS 0x40000000
65 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
66 #define CONFIG_PCI_MEM_SIZE 0x10000000
68 #define CONFIG_PCI_IO_BUS 0x50000000
69 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
70 #define CONFIG_PCI_IO_SIZE 0x01000000
72 #define CFG_XLB_PIPELINING 1
75 #define CONFIG_MAC_PARTITION
76 #define CONFIG_DOS_PARTITION
77 #define CONFIG_ISO_PARTITION
82 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
89 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
90 #include <cmd_confdefs.h>
92 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
94 #if (TEXT_BASE == 0xFFE00000) /* Boot low */
95 # define CFG_LOWBOOT 1
101 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
103 #define CONFIG_PREBOOT "echo;" \
104 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
107 #undef CONFIG_BOOTARGS
109 #define CONFIG_EXTRA_ENV_SETTINGS \
111 "nfsargs=setenv bootargs root=/dev/nfs rw " \
112 "nfsroot=$(serverip):$(rootpath)\0" \
113 "ramargs=setenv bootargs root=/dev/ram rw\0" \
114 "addip=setenv bootargs $(bootargs) " \
115 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
116 ":$(hostname):$(netdev):off panic=1\0" \
117 "flash_nfs=run nfsargs addip;" \
118 "bootm $(kernel_addr)\0" \
119 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
120 "rootpath=/opt/eldk/ppc_82xx\0" \
123 #define CONFIG_BOOTCOMMAND "run net_nfs"
126 * IPB Bus clocking configuration.
128 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
131 * Flash configuration
133 #define CFG_FLASH_BASE 0xFFE00000
135 #define CFG_FLASH_SIZE 0x00200000 /* 2 MByte */
136 #define CFG_MAX_FLASH_SECT 35 /* max num of sects on one chip */
138 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) /* second sector */
139 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
141 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
142 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
145 * Environment settings
147 #define CFG_ENV_IS_IN_FLASH 1
148 #define CFG_ENV_SIZE 0x2000
149 #define CFG_ENV_SECT_SIZE 0x2000
150 #define CONFIG_ENV_OVERWRITE 1
155 #define CFG_MBAR 0xF0000000
156 #define CFG_SDRAM_BASE 0x00000000
157 #define CFG_DEFAULT_MBAR 0x80000000
159 #define CONFIG_MPC5200_DDR
161 /* Use ON-Chip SRAM until RAM will be available */
162 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
164 /* preserve space for the post_word at end of on-chip SRAM */
165 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
167 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
171 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
172 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
173 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175 #define CFG_MONITOR_BASE TEXT_BASE
176 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
177 # define CFG_RAMBOOT 1
180 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
181 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
182 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
185 * Ethernet configuration
187 #define CONFIG_MPC5xxx_FEC 1
189 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
191 /* #define CONFIG_FEC_10MBIT 1 */
192 #define CONFIG_PHY_ADDR 0x00
197 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
198 * Bit 0 (mask: 0x80000000): 1
199 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
200 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
201 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
203 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
204 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
205 * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
206 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
209 #if defined (CONFIG_MINIFAP)
210 #define CFG_GPS_PORT_CONFIG 0x93000004
212 #define CFG_GPS_PORT_CONFIG 0x81001004
218 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
221 * Miscellaneous configurable options
223 #define CFG_LONGHELP /* undef to save memory */
224 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
225 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
226 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
228 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
230 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
231 #define CFG_MAXARGS 16 /* max number of command args */
232 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
234 /* Enable an alternate, more extensive memory test */
235 #define CFG_ALT_MEMTEST
237 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
238 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
240 #define CFG_LOAD_ADDR 0x100000 /* default load address */
242 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
245 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
246 * which is normally part of the default commands (CFV_CMD_DFL)
251 * Various low-level settings
253 #if defined(CONFIG_MPC5200)
254 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
255 #define CFG_HID0_FINAL HID0_ICE
257 #define CFG_HID0_INIT 0
258 #define CFG_HID0_FINAL 0
261 #define CFG_BOOTCS_START CFG_FLASH_BASE
262 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
263 #define CFG_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
264 #define CFG_CS0_START CFG_FLASH_BASE
265 #define CFG_CS0_SIZE CFG_FLASH_SIZE
267 /* 32Mbit SRAM @0x30000000 */
268 #define CFG_CS1_START 0x30000000
269 #define CFG_CS1_SIZE 0x00400000
270 #define CFG_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
272 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
273 #define CFG_CS2_START 0x80000000
274 #define CFG_CS2_SIZE 0x0001000
275 #define CFG_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
277 /* GPIO in @0x30400000 */
278 #define CFG_CS3_START 0x30400000
279 #define CFG_CS3_SIZE 0x00100000
280 #define CFG_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
282 #define CFG_CS_BURST 0x00000000
283 #define CFG_CS_DEADCYCLE 0x33333333
285 /*-----------------------------------------------------------------------
287 *-----------------------------------------------------------------------
289 #define CONFIG_USB_OHCI
290 #define CONFIG_USB_CLOCK 0x00015555
291 #define CONFIG_USB_CONFIG 0x00001000
292 #define CONFIG_USB_STORAGE
294 /*-----------------------------------------------------------------------
295 * IDE/ATA stuff Supports IDE harddisk
296 *-----------------------------------------------------------------------
299 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
301 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
302 #undef CONFIG_IDE_LED /* LED for ide not supported */
304 #define CONFIG_IDE_RESET /* reset for ide supported */
305 #define CONFIG_IDE_PREINIT
307 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
308 #define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
310 #define CFG_ATA_IDE0_OFFSET 0x0000
312 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
314 /* Offset for data I/O */
315 #define CFG_ATA_DATA_OFFSET (0x0060)
317 /* Offset for normal register accesses */
318 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
320 /* Offset for alternate registers */
321 #define CFG_ATA_ALT_OFFSET (0x005C)
323 /* Interval between registers */
324 #define CFG_ATA_STRIDE 4
326 #define CONFIG_ATAPI 1
328 #endif /* __CONFIG_H */