2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34 #define CONFIG_INKA4X0 1 /* INKA4x0 board */
36 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
38 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39 #define BOOTFLAG_WARM 0x02 /* Software reboot */
41 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
44 * Serial console configuration
46 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
47 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
52 * 0x40000000 - 0x4fffffff - PCI Memory
53 * 0x50000000 - 0x50ffffff - PCI IO Space
56 #define CONFIG_PCI_PNP 1
57 #define CONFIG_PCI_SCAN_SHOW 1
58 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
60 #define CONFIG_PCI_MEM_BUS 0x40000000
61 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
62 #define CONFIG_PCI_MEM_SIZE 0x10000000
64 #define CONFIG_PCI_IO_BUS 0x50000000
65 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
66 #define CONFIG_PCI_IO_SIZE 0x01000000
68 #define CFG_XLB_PIPELINING 1
71 #define CONFIG_MAC_PARTITION
72 #define CONFIG_DOS_PARTITION
73 #define CONFIG_ISO_PARTITION
79 #define CONFIG_BOOTP_BOOTFILESIZE
80 #define CONFIG_BOOTP_BOOTPATH
81 #define CONFIG_BOOTP_GATEWAY
82 #define CONFIG_BOOTP_HOSTNAME
86 * Command line configuration.
88 #include <config_cmd_default.h>
90 #define CONFIG_CMD_DHCP
91 #define CONFIG_CMD_EXT2
92 #define CONFIG_CMD_FAT
93 #define CONFIG_CMD_IDE
94 #define CONFIG_CMD_NFS
95 #define CONFIG_CMD_PCI
96 #define CONFIG_CMD_SNTP
97 #define CONFIG_CMD_USB
100 #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
102 #if (TEXT_BASE == 0xFFE00000) /* Boot low */
103 # define CFG_LOWBOOT 1
109 #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
111 #define CONFIG_PREBOOT "echo;" \
112 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
115 #undef CONFIG_BOOTARGS
117 #define CONFIG_ETHADDR 00:a0:a4:03:00:00
118 #define CONFIG_OVERWRITE_ETHADDR_ONCE
120 #define CONFIG_IPADDR 192.168.100.2
121 #define CONFIG_SERVERIP 192.168.100.1
122 #define CONFIG_NETMASK 255.255.255.0
123 #define HOSTNAME inka4x0
124 #define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage
125 #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
127 #define CONFIG_EXTRA_ENV_SETTINGS \
129 "nfsargs=setenv bootargs root=/dev/nfs rw " \
130 "nfsroot=${serverip}:${rootpath}\0" \
131 "ramargs=setenv bootargs root=/dev/ram rw\0" \
132 "addip=setenv bootargs ${bootargs} " \
133 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
134 ":${hostname}:${netdev}:off panic=1\0" \
135 "addcons=setenv bootargs ${bootargs} " \
136 "console=ttyS0,${baudrate}\0" \
137 "flash_nfs=run nfsargs addip addcons;" \
138 "bootm ${kernel_addr}\0" \
139 "net_nfs=tftp 200000 ${bootfile};" \
140 "run nfsargs addip addcons;bootm\0" \
141 "enable_disp=mw.l 100000 04000000 1;" \
142 "cp.l 100000 f0000b20 1;" \
143 "cp.l 100000 f0000b28 1\0" \
144 "ideargs=setenv bootargs root=/dev/hda1 rw\0" \
145 "ide_boot=ext2load ide 0:1 200000 uImage;" \
146 "run ideargs addip addcons enable_disp;bootm\0" \
150 #define CONFIG_BOOTCOMMAND "run ide_boot"
153 * IPB Bus clocking configuration.
155 #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
158 * Flash configuration
160 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
161 #define CFG_FLASH_CFI_DRIVER 1
162 #define CFG_FLASH_BASE 0xffe00000
163 #define CFG_FLASH_SIZE 0x00200000
164 #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
165 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
166 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
167 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
170 * Environment settings
172 #define CFG_ENV_IS_IN_FLASH 1
173 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
174 #define CFG_ENV_SIZE 0x2000
175 #define CFG_ENV_SECT_SIZE 0x2000
176 #define CONFIG_ENV_OVERWRITE 1
177 #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
182 #define CFG_MBAR 0xF0000000
183 #define CFG_SDRAM_BASE 0x00000000
184 #define CFG_DEFAULT_MBAR 0x80000000
187 * SDRAM controller configuration
189 #undef CONFIG_SDR_MT48LC16M16A2
190 #undef CONFIG_DDR_MT46V16M16
191 #undef CONFIG_DDR_MT46V32M16
192 #undef CONFIG_DDR_HYB25D512160BF
193 #define CONFIG_DDR_K4H511638C
195 /* Use ON-Chip SRAM until RAM will be available */
196 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
198 /* preserve space for the post_word at end of on-chip SRAM */
199 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
201 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
205 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
206 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
207 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
209 #define CFG_MONITOR_BASE TEXT_BASE
210 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
211 # define CFG_RAMBOOT 1
214 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
215 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
216 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
219 * Ethernet configuration
221 #define CONFIG_MPC5xxx_FEC 1
223 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
225 /* #define CONFIG_FEC_10MBIT 1 */
226 #define CONFIG_PHY_ADDR 0x00
232 * use CS1 as gpio_wkup_6 output
233 * Bit 0 (mask: 0x80000000): 0
234 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
235 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
236 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
238 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
239 * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
240 * 011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
242 #define CFG_GPS_PORT_CONFIG 0x01001004
247 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
250 * Miscellaneous configurable options
252 #define CFG_LONGHELP /* undef to save memory */
253 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
254 #if defined(CONFIG_CMD_KGDB)
255 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
257 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
259 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
260 #define CFG_MAXARGS 16 /* max number of command args */
261 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
263 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
264 #if defined(CONFIG_CMD_KGDB)
265 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
268 /* Enable an alternate, more extensive memory test */
269 #define CFG_ALT_MEMTEST
271 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
272 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
274 #define CFG_LOAD_ADDR 0x100000 /* default load address */
276 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
279 * Enable loopw command.
284 * Various low-level settings
286 #if defined(CONFIG_MPC5200)
287 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
288 #define CFG_HID0_FINAL HID0_ICE
290 #define CFG_HID0_INIT 0
291 #define CFG_HID0_FINAL 0
294 #define CFG_BOOTCS_START CFG_FLASH_BASE
295 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
296 #define CFG_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
297 #define CFG_CS0_START CFG_FLASH_BASE
298 #define CFG_CS0_SIZE CFG_FLASH_SIZE
300 /* 32Mbit SRAM @0x30000000 */
301 #define CFG_CS1_START 0x30000000
302 #define CFG_CS1_SIZE 0x00400000
303 #define CFG_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
305 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
306 #define CFG_CS2_START 0x80000000
307 #define CFG_CS2_SIZE 0x0001000
308 #define CFG_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
310 /* GPIO in @0x30400000 */
311 #define CFG_CS3_START 0x30400000
312 #define CFG_CS3_SIZE 0x00100000
313 #define CFG_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
315 #define CFG_CS_BURST 0x00000000
316 #define CFG_CS_DEADCYCLE 0x33333333
318 /*-----------------------------------------------------------------------
320 *-----------------------------------------------------------------------
322 #define CONFIG_USB_OHCI
323 #define CONFIG_USB_CLOCK 0x00015555
324 #define CONFIG_USB_CONFIG 0x00001000
325 #define CONFIG_USB_STORAGE
327 /*-----------------------------------------------------------------------
328 * IDE/ATA stuff Supports IDE harddisk
329 *-----------------------------------------------------------------------
332 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
334 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
335 #undef CONFIG_IDE_LED /* LED for ide not supported */
337 #define CONFIG_IDE_RESET /* reset for ide supported */
338 #define CONFIG_IDE_PREINIT
340 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
341 #define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
343 #define CFG_ATA_IDE0_OFFSET 0x0000
344 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
345 #define CFG_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
346 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */
347 #define CFG_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
348 #define CFG_ATA_STRIDE 4 /* Interval between registers */
350 #define CONFIG_ATAPI 1
352 #define CFG_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
354 #endif /* __CONFIG_H */