2 * (C) Copyright 2000, 2001, 2002
3 * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
5 * Configuration for the Auerswald Innokom CPU board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * include/configs/innokom.h - configuration options, board specific
34 * If we are developing, we might want to start U-Boot from ram
35 * so we MUST NOT initialize critical regs like mem-timing ...
37 #define CONFIG_INIT_CRITICAL /* undef for developing */
40 * High Level Configuration Options
43 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
44 #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
46 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
47 /* for timer/console/ethernet */
53 * select serial console configuration
55 #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
57 /* allow to overwrite serial and ethaddr */
58 #define CONFIG_ENV_OVERWRITE
60 #define CONFIG_BAUDRATE 19200
61 #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
63 #define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE)
64 /* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
65 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
66 #include <cmd_confdefs.h>
68 #define CONFIG_BOOTDELAY 3
69 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
70 #define CONFIG_BOOTARGS "console=ttyS0,19200"
71 #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
72 #define CONFIG_NETMASK 255.255.255.0
73 #define CONFIG_IPADDR 192.168.1.56
74 #define CONFIG_SERVERIP 192.168.1.2
75 #define CONFIG_BOOTCOMMAND "bootm 0x40000"
76 #define CONFIG_SHOW_BOOT_PROGRESS
78 #define CONFIG_CMDLINE_TAG 1
81 * Miscellaneous configurable options
85 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
86 * used for the RAM copy of the uboot code
89 #define CFG_MALLOC_LEN (256*1024)
90 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
92 #define CFG_LONGHELP /* undef to save memory */
93 #define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
94 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
95 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
96 #define CFG_MAXARGS 16 /* max number of command args */
97 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
99 #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
100 #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
102 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
104 #define CFG_LOAD_ADDR 0xa3000000 /* load kernel to this address */
106 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
107 /* RS: the oscillator is actually 3680130?? */
109 #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
111 /* ^^^^^ Memory Speed 99.53 MHz */
112 /* ^^ Run Mode Speed = 2x Mem Speed */
113 /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
115 #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
117 /* valid baudrates */
118 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
123 #define CONFIG_HARD_I2C 1
124 #define CFG_I2C_SPEED 50000
125 #define CFG_I2C_SLAVE 0xfe
127 #define CFG_ENV_IS_IN_EEPROM 1
129 #define CFG_ENV_OFFSET 0x00 /* environment starts here */
130 #define CFG_ENV_SIZE 1024 /* 1 KiB */
131 #define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
132 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
133 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
134 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */
135 #define CFG_EEPROM_SIZE 4096 /* size in bytes */
136 #define CFG_I2C_INIT_BOARD 1 /* board has it's own init */
139 * SMSC91C111 Network Card
141 #define CONFIG_DRIVER_SMC91111 1
142 #define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
143 #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
144 #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
145 #undef CONFIG_SHOW_ACTIVITY
146 #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
151 * The stack sizes are set up in start.S using the settings below
153 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
154 #ifdef CONFIG_USE_IRQ
155 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
156 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
160 * Physical Memory Map
162 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
163 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
164 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
166 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
167 #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
169 #define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
170 #define CFG_DRAM_SIZE 0x04000000
172 #define CFG_FLASH_BASE PHYS_FLASH_1
178 #define CFG_JFFS_CUSTOM_PART 1 /* see board/innokom/flash.c */
179 #define CONFIG_MTD_INNOKOM_16MB 1 /* development flash */
180 #undef CONFIG_MTD_INNOKOM_64MB /* production flash */
195 * GP63 == TDM_OE is 1
200 #define CFG_GPSR0_VAL 0x03008000
201 #define CFG_GPSR1_VAL 0xC0028282
202 #define CFG_GPSR2_VAL 0x0001C000
204 /* GP02 == DON_RST is 0
206 * GP45 == USB_ACT is 0
209 * GP73 == SWUPD_LED is 0
211 #define CFG_GPCR0_VAL 0x00800004
212 #define CFG_GPCR1_VAL 0x30002000
213 #define CFG_GPCR2_VAL 0x00000100
215 /* GP00 == DON_READY is input
216 * GP01 == DON_OK is input
217 * GP02 == DON_RST is output
218 * GP03 == RESET_IND is input
219 * GP07 == RES11 is input
220 * GP09 == RES12 is input
221 * GP11 == SWUPDATE is input
222 * GP14 == nPOWEROK is input
223 * GP15 == nCS1 is output
224 * GP17 == RES22 is input
225 * GP18 == RDY is input
226 * GP23 == SCLK is output
227 * GP24 == SFRM is output
228 * GP25 == TXD is output
229 * GP26 == RXD is input
230 * GP32 == RES21 is input
231 * GP33 == nCS5 is output
232 * GP34 == FFRXD is input
233 * GP35 == CTS is input
234 * GP39 == FFTXD is output
235 * GP41 == RTS is output
236 * GP42 == USB_OK is input
237 * GP45 == USB_ACT is output
238 * GP46 == RXD is input
239 * GP47 == TXD is output
240 * GP49 == nPWE is output
241 * GP58 == nCPUBUSINT is input
242 * GP59 == LANINT is input
243 * GP60 == PLLEN is output
244 * GP61 == LED_A is output
245 * GP62 == LED_B is output
246 * GP63 == TDM_OE is output
247 * GP64 == nDSPINT is input
248 * GP65 == STRAP0 is input
249 * GP67 == STRAP1 is input
250 * GP69 == STRAP2 is input
251 * GP70 == STRAP3 is input
252 * GP71 == STRAP4 is input
253 * GP73 == SWUPD_LED is output
254 * GP78 == nCS2 is output
255 * GP79 == nCS3 is output
256 * GP80 == nCS4 is output
258 #define CFG_GPDR0_VAL 0x03808004
259 #define CFG_GPDR1_VAL 0xF002A282
260 #define CFG_GPDR2_VAL 0x0001C200
262 /* GP15 == nCS1 is AF10
263 * GP18 == RDY is AF01
264 * GP23 == SCLK is AF10
265 * GP24 == SFRM is AF10
266 * GP25 == TXD is AF10
267 * GP26 == RXD is AF01
268 * GP33 == nCS5 is AF10
269 * GP34 == FFRXD is AF01
270 * GP35 == CTS is AF01
271 * GP39 == FFTXD is AF10
272 * GP41 == RTS is AF10
273 * GP46 == RXD is AF10
274 * GP47 == TXD is AF01
275 * GP49 == nPWE is AF10
276 * GP78 == nCS2 is AF10
277 * GP79 == nCS3 is AF10
278 * GP80 == nCS4 is AF10
280 #define CFG_GAFR0_L_VAL 0x80000000
281 #define CFG_GAFR0_U_VAL 0x001A8010
282 #define CFG_GAFR1_L_VAL 0x60088058
283 #define CFG_GAFR1_U_VAL 0x00000008
284 #define CFG_GAFR2_L_VAL 0xA0000000
285 #define CFG_GAFR2_U_VAL 0x00000002
288 /* FIXME: set GPIO_RER/FER */
296 #define CFG_PSSR_VAL 0x37
301 * This is the configuration for nCS0/1 -> flash banks
302 * configuration for nCS1:
303 * [31] 0 - Slower Device
304 * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
305 * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
306 * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
307 * [19] 1 - 16 Bit bus width
308 * [18:16] 000 - nonburst RAM or FLASH
309 * configuration for nCS0:
310 * [15] 0 - Slower Device
311 * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
312 * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
313 * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
314 * [03] 1 - 16 Bit bus width
315 * [02:00] 000 - nonburst RAM or FLASH
317 #define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
319 /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
320 * configuration for nCS3: DSP
321 * [31] 0 - Slower Device
322 * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
323 * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
324 * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
325 * [19] 1 - 16 Bit bus width
326 * [18:16] 100 - variable latency I/O
327 * configuration for nCS2: TDM-Switch
328 * [15] 0 - Slower Device
329 * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
330 * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
331 * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
332 * [03] 1 - 16 Bit bus width
333 * [02:00] 100 - variable latency I/O
335 #define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */
337 /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
339 * configuration for nCS5: LAN Controller
340 * [31] 0 - Slower Device
341 * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
342 * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
343 * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
344 * [19] 1 - 16 Bit bus width
345 * [18:16] 100 - variable latency I/O
346 * configuration for nCS4: ExtBus
347 * [15] 0 - Slower Device
348 * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
349 * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
350 * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
351 * [03] 1 - 16 Bit bus width
352 * [02:00] 100 - variable latency I/O
354 #define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
356 /* MDCNFG: SDRAM Configuration Register
358 * [31:29] 000 - reserved
359 * [28] 0 - no SA1111 compatiblity mode
360 * [27] 0 - latch return data with return clock
361 * [26] 0 - alternate addressing for pair 2/3
362 * [25:24] 00 - timings
363 * [23] 0 - internal banks in lower partition 2/3 (not used)
364 * [22:21] 00 - row address bits for partition 2/3 (not used)
365 * [20:19] 00 - column address bits for partition 2/3 (not used)
366 * [18] 0 - SDRAM partition 2/3 width is 32 bit
367 * [17] 0 - SDRAM partition 3 disabled
368 * [16] 0 - SDRAM partition 2 disabled
369 * [15:13] 000 - reserved
370 * [12] 1 - SA1111 compatiblity mode
371 * [11] 1 - latch return data with return clock
372 * [10] 0 - no alternate addressing for pair 0/1
373 * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
374 * [7] 1 - 4 internal banks in lower partition pair
375 * [06:05] 10 - 13 row address bits for partition 0/1
376 * [04:03] 01 - 9 column address bits for partition 0/1
377 * [02] 0 - SDRAM partition 0/1 width is 32 bit
378 * [01] 0 - disable SDRAM partition 1
379 * [00] 1 - enable SDRAM partition 0
381 /* use the configuration above but disable partition 0 */
382 #define CFG_MDCNFG_VAL 0x000019c8
384 /* MDREFR: SDRAM Refresh Control Register
386 * [32:26] 0 - reserved
387 * [25] 0 - K2FREE: not free running
388 * [24] 0 - K1FREE: not free running
389 * [23] 1 - K0FREE: not free running
390 * [22] 0 - SLFRSH: self refresh disabled
392 * [20] 0 - APD: no auto power down
393 * [19] 0 - K2DB2: SDCLK2 is MemClk
394 * [18] 0 - K2RUN: disable SDCLK2
395 * [17] 0 - K1DB2: SDCLK1 is MemClk
396 * [16] 1 - K1RUN: enable SDCLK1
397 * [15] 1 - E1PIN: SDRAM clock enable
398 * [14] 1 - K0DB2: SDCLK0 is MemClk
399 * [13] 0 - K0RUN: disable SDCLK0
400 * [12] 1 - E0PIN: disable SDCKE0
401 * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
403 #define CFG_MDREFR_VAL 0x0081D018
405 /* MDMRS: Mode Register Set Configuration Register
408 * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
409 * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
410 * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
411 * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
413 * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
414 * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
415 * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
416 * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
418 #define CFG_MDMRS_VAL 0x00020022
421 * PCMCIA and CF Interfaces
423 #define CFG_MECR_VAL 0x00000000
424 #define CFG_MCMEM0_VAL 0x00000000
425 #define CFG_MCMEM1_VAL 0x00000000
426 #define CFG_MCATT0_VAL 0x00000000
427 #define CFG_MCATT1_VAL 0x00000000
428 #define CFG_MCIO0_VAL 0x00000000
429 #define CFG_MCIO1_VAL 0x00000000
432 #define CSB226_USER_LED0 0x00000008
433 #define CSB226_USER_LED1 0x00000010
434 #define CSB226_USER_LED2 0x00000020
438 * FLASH and environment organization
440 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
441 #define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
443 /* timeout values are in ticks */
444 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
445 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
447 #endif /* __CONFIG_H */