4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
9 * Philippe Robin, <philippe.robin@arm.com>
10 * Configuration for Integrator AP board.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * High Level Configuration Options
37 #define CFG_MEMTEST_START 0x100000
38 #define CFG_MEMTEST_END 0x10000000
40 #define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */
41 #define CFG_TIMERBASE 0x13000100 /* Timer1 */
43 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
44 #define CONFIG_SETUP_MEMORY_TAGS 1
45 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
47 * Size of malloc() pool
49 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
50 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
55 #define CFG_PL010_SERIAL
56 #define CONFIG_CONS_INDEX 0
57 #define CONFIG_BAUDRATE 38400
58 #define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) }
59 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
60 #define CFG_SERIAL0 0x16000000
61 #define CFG_SERIAL1 0x17000000
63 /*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */
64 /*#define CONFIG_NET_MULTI */
65 /*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
67 #define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY)
70 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
71 #include <cmd_confdefs.h>
73 #define CONFIG_BOOTDELAY 2
74 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty"
75 #define CONFIG_BOOTCOMMAND ""
78 * Miscellaneous configurable options
80 #define CFG_LONGHELP /* undef to save memory */
81 #define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */
82 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
83 /* Print Buffer Size */
84 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
85 #define CFG_MAXARGS 16 /* max number of command args */
86 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
88 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
89 #define CFG_LOAD_ADDR 0x7fc0 /* default load address */
91 /*-----------------------------------------------------------------------
94 * The stack sizes are set up in start.S using the settings below
96 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
98 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
99 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
102 /*-----------------------------------------------------------------------
103 * Physical Memory Map
105 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
106 #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
107 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
109 #define CFG_FLASH_BASE 0x24000000
111 /*-----------------------------------------------------------------------
112 * FLASH and environment organization
114 #define CFG_ENV_IS_NOWHERE
115 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
116 #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
117 /* timeout values are in ticks */
118 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
119 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
120 #define CFG_MAX_FLASH_SECT 128
121 #define CFG_ENV_SIZE 32768
123 #define PHYS_FLASH_1 (CFG_FLASH_BASE)
125 /*-----------------------------------------------------------------------
129 /*#define CONFIG_PCI /--* include pci support */
130 #undef CONFIG_PCI_PNP
131 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
134 #define CONFIG_EEPRO100
135 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
138 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000
139 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
142 #define INTEGRATOR_PCI_BASE 0x40000000
143 #define INTEGRATOR_PCI_SIZE 0x3FFFFFFF
145 /* memory map as seen by the CPU on the local bus */
146 #define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */
147 #define CPU_PCI_IO_SIZE 0x10000
149 #define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */
150 #define CPU_PCI_CNFG_SIZE 0x1000000
152 #define PCI_MEM_BASE 0x40000000 /* 512M to xxx */
153 /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
154 #define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */
155 /* unused (128-16)M from B1000000-B7FFFFFF */
156 #define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
157 /* unused ((128-16)M - 64K) from XXX */
159 #define PCI_V3_BASE 0x62000000
161 /* V3 PCI bridge controller */
162 #define V3_BASE 0x62000000 /* V360EPC registers */
164 #define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS)
165 #define PCI_ENET0_MEMADDR (PCI_MEM_BASE)
168 #define V3_PCI_VENDOR 0x00000000
169 #define V3_PCI_DEVICE 0x00000002
170 #define V3_PCI_CMD 0x00000004
171 #define V3_PCI_STAT 0x00000006
172 #define V3_PCI_CC_REV 0x00000008
173 #define V3_PCI_HDR_CF 0x0000000C
174 #define V3_PCI_IO_BASE 0x00000010
175 #define V3_PCI_BASE0 0x00000014
176 #define V3_PCI_BASE1 0x00000018
177 #define V3_PCI_SUB_VENDOR 0x0000002C
178 #define V3_PCI_SUB_ID 0x0000002E
179 #define V3_PCI_ROM 0x00000030
180 #define V3_PCI_BPARAM 0x0000003C
181 #define V3_PCI_MAP0 0x00000040
182 #define V3_PCI_MAP1 0x00000044
183 #define V3_PCI_INT_STAT 0x00000048
184 #define V3_PCI_INT_CFG 0x0000004C
185 #define V3_LB_BASE0 0x00000054
186 #define V3_LB_BASE1 0x00000058
187 #define V3_LB_MAP0 0x0000005E
188 #define V3_LB_MAP1 0x00000062
189 #define V3_LB_BASE2 0x00000064
190 #define V3_LB_MAP2 0x00000066
191 #define V3_LB_SIZE 0x00000068
192 #define V3_LB_IO_BASE 0x0000006E
193 #define V3_FIFO_CFG 0x00000070
194 #define V3_FIFO_PRIORITY 0x00000072
195 #define V3_FIFO_STAT 0x00000074
196 #define V3_LB_ISTAT 0x00000076
197 #define V3_LB_IMASK 0x00000077
198 #define V3_SYSTEM 0x00000078
199 #define V3_LB_CFG 0x0000007A
200 #define V3_PCI_CFG 0x0000007C
201 #define V3_DMA_PCI_ADR0 0x00000080
202 #define V3_DMA_PCI_ADR1 0x00000090
203 #define V3_DMA_LOCAL_ADR0 0x00000084
204 #define V3_DMA_LOCAL_ADR1 0x00000094
205 #define V3_DMA_LENGTH0 0x00000088
206 #define V3_DMA_LENGTH1 0x00000098
207 #define V3_DMA_CSR0 0x0000008B
208 #define V3_DMA_CSR1 0x0000009B
209 #define V3_DMA_CTLB_ADR0 0x0000008C
210 #define V3_DMA_CTLB_ADR1 0x0000009C
211 #define V3_DMA_DELAY 0x000000E0
212 #define V3_MAIL_DATA 0x000000C0
213 #define V3_PCI_MAIL_IEWR 0x000000D0
214 #define V3_PCI_MAIL_IERD 0x000000D2
215 #define V3_LB_MAIL_IEWR 0x000000D4
216 #define V3_LB_MAIL_IERD 0x000000D6
217 #define V3_MAIL_WR_STAT 0x000000D8
218 #define V3_MAIL_RD_STAT 0x000000DA
219 #define V3_QBA_MAP 0x000000DC
221 /* SYSTEM register bits */
222 #define V3_SYSTEM_M_RST_OUT (1 << 15)
223 #define V3_SYSTEM_M_LOCK (1 << 14)
226 #define V3_PCI_CFG_M_RETRY_EN (1 << 10)
227 #define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
228 #define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
230 /* PCI MAP register bits (PCI -> Local bus) */
231 #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
232 #define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
233 #define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10)
234 #define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8)
235 #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
236 #define V3_PCI_MAP_M_REG_EN (1 << 1)
237 #define V3_PCI_MAP_M_ENABLE (1 << 0)
239 /* 9 => 512M window size */
240 #define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
242 /* A => 1024M window size */
243 #define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
245 /* LB_BASE register bits (Local bus -> PCI) */
246 #define V3_LB_BASE_M_MAP_ADR 0xFFF00000
247 #define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9)
248 #define V3_LB_BASE_M_ADR_SIZE 0x000000F0
249 #define V3_LB_BASE_M_PREFETCH (1 << 3)
250 #define V3_LB_BASE_M_ENABLE (1 << 0)
252 /* PCI COMMAND REGISTER bits */
253 #define V3_COMMAND_M_FBB_EN (1 << 9)
254 #define V3_COMMAND_M_SERR_EN (1 << 8)
255 #define V3_COMMAND_M_PAR_EN (1 << 6)
256 #define V3_COMMAND_M_MASTER_EN (1 << 2)
257 #define V3_COMMAND_M_MEM_EN (1 << 1)
258 #define V3_COMMAND_M_IO_EN (1 << 0)
260 #define INTEGRATOR_SC_BASE 0x11000000
261 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
262 #define INTEGRATOR_SC_PCIENABLE \
263 (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
265 /*-----------------------------------------------------------------------
266 * There are various dependencies on the core module (CM) fitted
267 * Users should refer to their CM user guide
268 * - when porting adjust u-boot/Makefile accordingly
269 * to define the necessary CONFIG_ s for the CM involved
270 * see e.g. integratorcp_CM926EJ-S_config
273 #define CM_BASE 0x10000000
275 /* CM registers common to all integrator/CP CMs */
276 #define OS_CTRL 0x0000000C
277 #define CMMASK_REMAP 0x00000005 /* Set remap & led */
278 #define CMMASK_RESET 0x00000008
279 #define OS_LOCK 0x00000014
280 #define CMVAL_LOCK 0x0000A000 /* Locking value */
281 #define CMMASK_LOCK 0x0000005F /* Locking value */
282 #define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */
283 #define OS_SDRAM 0x00000020
284 #define OS_INIT 0x00000024
285 #define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
286 #define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
288 #ifdef CONFIG_CM_SPD_DETECT
289 #define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
292 #endif /* __CONFIG_H */