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1 /*
2  * (C) Copyright 2007
3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
4  *
5  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25
26 /************************************************************************
27  * katmai.h - configuration for AMCC Katmai (440SPe)
28  ***********************************************************************/
29
30 #ifndef __CONFIG_H
31 #define __CONFIG_H
32
33 /*-----------------------------------------------------------------------
34  * High Level Configuration Options
35  *----------------------------------------------------------------------*/
36 #define CONFIG_KATMAI                   1       /* Board is Katmai      */
37 #define CONFIG_4xx                      1       /* ... PPC4xx family    */
38 #define CONFIG_440                      1       /* ... PPC440 family    */
39 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
40 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
41 #define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
42
43 /*
44  * Enable this board for more than 2GB of SDRAM
45  */
46 #define CONFIG_PHYS_64BIT
47 #define CONFIG_VERY_BIG_RAM
48 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)2 << 30)
49
50 /*
51  * Include common defines/options for all AMCC eval boards
52  */
53 #define CONFIG_HOSTNAME         katmai
54 #include "amcc-common.h"
55
56 /*
57  * For booting 256K-paged Linux we should have 16MB of memory
58  * for Linux initial memory map
59  */
60 #undef CONFIG_SYS_BOOTMAPSZ
61 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)
62
63 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_pre_init          */
64 #undef  CONFIG_SHOW_BOOT_PROGRESS
65
66 /*-----------------------------------------------------------------------
67  * Base addresses -- Note these are effective addresses where the
68  * actual resources get mapped (not physical addresses)
69  *----------------------------------------------------------------------*/
70 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH       */
71 #define CONFIG_SYS_PERIPHERAL_BASE      0xa0000000      /* internal peripherals */
72 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
73
74 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
75 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
76 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
77
78 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
79 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
80 #define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
81
82 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
83 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
84 #define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
85 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
86 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
87 #define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
88
89 /* base address of inbound PCIe window */
90 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
91
92 /* System RAM mapped to PCI space */
93 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
94 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
95 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
96
97 #define CONFIG_SYS_ACE_BASE             0xfe000000      /* Xilinx ACE controller - Compact Flash */
98
99 /*-----------------------------------------------------------------------
100  * Initial RAM & stack pointer (placed in internal SRAM)
101  *----------------------------------------------------------------------*/
102 #define CONFIG_SYS_TEMP_STACK_OCM       1
103 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
104 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
105 #define CONFIG_SYS_INIT_RAM_END 0x2000          /* End of used area in RAM */
106 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
107
108 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
109 #define CONFIG_SYS_POST_WORD_ADDR       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
110 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_POST_WORD_ADDR
111
112 /*-----------------------------------------------------------------------
113  * Serial Port
114  *----------------------------------------------------------------------*/
115 #undef CONFIG_UART1_CONSOLE
116 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
117
118 /*-----------------------------------------------------------------------
119  * DDR SDRAM
120  *----------------------------------------------------------------------*/
121 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
122 #define SPD_EEPROM_ADDRESS      {0x51, 0x52}    /* SPD i2c spd addresses*/
123 #define CONFIG_DDR_ECC          1       /* with ECC support             */
124 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* optimal value found by GDA*/
125 #undef  CONFIG_STRESS
126
127 /*-----------------------------------------------------------------------
128  * I2C
129  *----------------------------------------------------------------------*/
130 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
131
132 #define CONFIG_I2C_MULTI_BUS
133 #define CONFIG_I2C_CMD_TREE
134 #define CONFIG_SYS_SPD_BUS_NUM          0       /* The I2C bus for SPD          */
135
136 #define IIC0_BOOTPROM_ADDR      0x50
137 #define IIC0_ALT_BOOTPROM_ADDR  0x54
138
139 #define CONFIG_SYS_I2C_MULTI_EEPROMS
140 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0x50)
141 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
142 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
143 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
144
145 /* I2C RTC */
146 #define CONFIG_RTC_M41T11       1
147 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC          */
148 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
149 #define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* play along with linux        */
150
151 /* I2C DTT */
152 #define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support  */
153 #define CONFIG_SYS_DTT_BUS_NUM          1       /* The I2C bus for DTT          */
154 /*
155  * standard dtt sensor configuration - bottom bit will determine local or
156  * remote sensor of the ADM1021, the rest determines index into
157  * CONFIG_SYS_DTT_ADM1021 array below.
158  */
159 #define CONFIG_DTT_SENSORS      { 0, 1 }
160
161 /*
162  * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
163  * there will be one entry in this array for each two (dummy) sensors in
164  * CONFIG_DTT_SENSORS.
165  *
166  * For Katmai board:
167  * - only one ADM1021
168  * - i2c addr 0x18
169  * - conversion rate 0x02 = 0.25 conversions/second
170  * - ALERT ouput disabled
171  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
172  * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
173  */
174 #define CONFIG_SYS_DTT_ADM1021          { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
175
176 /*-----------------------------------------------------------------------
177  * Environment
178  *----------------------------------------------------------------------*/
179 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
180
181 /*
182  * Default environment variables
183  */
184 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
185         CONFIG_AMCC_DEF_ENV                                             \
186         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
187         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
188         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
189         "kernel_addr=fff10000\0"                                        \
190         "ramdisk_addr=fff20000\0"                                       \
191         "kozio=bootm ffc60000\0"                                        \
192         "pciconfighost=1\0"                                             \
193         "pcie_mode=RP:RP:RP\0"                                          \
194         ""
195
196 /*
197  * Commands additional to the ones defined in amcc-common.h
198  */
199 #define CONFIG_CMD_EXT2
200 #define CONFIG_CMD_DATE
201 #define CONFIG_CMD_PCI
202 #define CONFIG_CMD_SDRAM
203 #define CONFIG_CMD_SNTP
204
205 #define CONFIG_IBM_EMAC4_V4     1       /* 440SPe has this EMAC version */
206 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
207 #define CONFIG_HAS_ETH0
208 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
209 #define CONFIG_PHY_RESET_DELAY  1000
210 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
211 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
212
213 /*-----------------------------------------------------------------------
214  * FLASH related
215  *----------------------------------------------------------------------*/
216 #define CONFIG_SYS_FLASH_CFI
217 #define CONFIG_FLASH_CFI_DRIVER
218 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
219 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
220
221 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
222 #define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
223 #define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
224
225 #undef  CONFIG_SYS_FLASH_CHECKSUM
226 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
227 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
228
229 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
230 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
231 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
232
233 /* Address and size of Redundant Environment Sector     */
234 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
235 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
236
237 /*-----------------------------------------------------------------------
238  * PCI stuff
239  *-----------------------------------------------------------------------
240  */
241 /* General PCI */
242 #define CONFIG_PCI                      /* include pci support          */
243 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
244 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
245 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
246
247 /* Board-specific PCI */
248 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
249 #undef  CONFIG_SYS_PCI_MASTER_INIT
250
251 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
252 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
253 /* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
254
255 /*
256  *  NETWORK Support (PCI):
257  */
258 /* Support for Intel 82557/82559/82559ER chips. */
259 #define CONFIG_EEPRO100
260
261 /*-----------------------------------------------------------------------
262  * Xilinx System ACE support
263  *----------------------------------------------------------------------*/
264 #define CONFIG_SYSTEMACE        1       /* Enable SystemACE support     */
265 #define CONFIG_SYS_SYSTEMACE_WIDTH      16      /* Data bus width is 16         */
266 #define CONFIG_SYS_SYSTEMACE_BASE       CONFIG_SYS_ACE_BASE
267 #define CONFIG_DOS_PARTITION    1
268
269 /*-----------------------------------------------------------------------
270  * External Bus Controller (EBC) Setup
271  *----------------------------------------------------------------------*/
272
273 /* Memory Bank 0 (Flash) initialization                                 */
274 #define CONFIG_SYS_EBC_PB0AP            (EBC_BXAP_BME_DISABLED      |           \
275                                  EBC_BXAP_TWT_ENCODE(7)     |           \
276                                  EBC_BXAP_BCE_DISABLE       |           \
277                                  EBC_BXAP_BCT_2TRANS        |           \
278                                  EBC_BXAP_CSN_ENCODE(0)     |           \
279                                  EBC_BXAP_OEN_ENCODE(0)     |           \
280                                  EBC_BXAP_WBN_ENCODE(0)     |           \
281                                  EBC_BXAP_WBF_ENCODE(0)     |           \
282                                  EBC_BXAP_TH_ENCODE(0)      |           \
283                                  EBC_BXAP_RE_DISABLED       |           \
284                                  EBC_BXAP_SOR_DELAYED       |           \
285                                  EBC_BXAP_BEM_WRITEONLY     |           \
286                                  EBC_BXAP_PEN_DISABLED)
287 #define CONFIG_SYS_EBC_PB0CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |   \
288                                  EBC_BXCR_BS_16MB                    |  \
289                                  EBC_BXCR_BU_RW                      |  \
290                                  EBC_BXCR_BW_16BIT)
291
292 /* Memory Bank 1 (Xilinx System ACE controller) initialization          */
293 #define CONFIG_SYS_EBC_PB1AP            (EBC_BXAP_BME_DISABLED      |           \
294                                  EBC_BXAP_TWT_ENCODE(4)     |           \
295                                  EBC_BXAP_BCE_DISABLE       |           \
296                                  EBC_BXAP_BCT_2TRANS        |           \
297                                  EBC_BXAP_CSN_ENCODE(0)     |           \
298                                  EBC_BXAP_OEN_ENCODE(0)     |           \
299                                  EBC_BXAP_WBN_ENCODE(0)     |           \
300                                  EBC_BXAP_WBF_ENCODE(0)     |           \
301                                  EBC_BXAP_TH_ENCODE(0)      |           \
302                                  EBC_BXAP_RE_DISABLED       |           \
303                                  EBC_BXAP_SOR_NONDELAYED    |           \
304                                  EBC_BXAP_BEM_WRITEONLY     |           \
305                                  EBC_BXAP_PEN_DISABLED)
306 #define CONFIG_SYS_EBC_PB1CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |    \
307                                  EBC_BXCR_BS_1MB                    |   \
308                                  EBC_BXCR_BU_RW                     |   \
309                                  EBC_BXCR_BW_16BIT)
310
311 /*-------------------------------------------------------------------------
312  * Initialize EBC CONFIG -
313  * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
314  * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
315  *-------------------------------------------------------------------------*/
316 #define CONFIG_SYS_EBC_CFG              (EBC_CFG_LE_UNLOCK    | \
317                                  EBC_CFG_PTD_ENABLE   | \
318                                  EBC_CFG_RTC_16PERCLK | \
319                                  EBC_CFG_ATC_PREVIOUS | \
320                                  EBC_CFG_DTC_PREVIOUS | \
321                                  EBC_CFG_CTC_PREVIOUS | \
322                                  EBC_CFG_OEO_PREVIOUS | \
323                                  EBC_CFG_EMC_DEFAULT  | \
324                                  EBC_CFG_PME_DISABLE  | \
325                                  EBC_CFG_PR_16)
326
327 /*-----------------------------------------------------------------------
328  * GPIO Setup
329  *----------------------------------------------------------------------*/
330 #define CONFIG_SYS_GPIO_PCIE_PRESENT0   17
331 #define CONFIG_SYS_GPIO_PCIE_PRESENT1   21
332 #define CONFIG_SYS_GPIO_PCIE_PRESENT2   23
333 #define CONFIG_SYS_GPIO_RS232_FORCEOFF  30
334
335 #define CONFIG_SYS_PFC0         (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
336                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
337                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
338                                  GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
339 #define CONFIG_SYS_GPIO_OR              GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
340 #define CONFIG_SYS_GPIO_TCR             GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
341 #define CONFIG_SYS_GPIO_ODR             0
342
343 #endif  /* __CONFIG_H */