3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 /************************************************************************
27 * katmai.h - configuration for AMCC Katmai (440SPe)
28 ***********************************************************************/
33 /*-----------------------------------------------------------------------
34 * High Level Configuration Options
35 *----------------------------------------------------------------------*/
36 #define CONFIG_KATMAI 1 /* Board is Katmai */
37 #define CONFIG_4xx 1 /* ... PPC4xx family */
38 #define CONFIG_440 1 /* ... PPC440 family */
39 #define CONFIG_440SPE 1 /* Specifc SPe support */
40 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
42 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
43 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
44 #undef CONFIG_SHOW_BOOT_PROGRESS
46 /*-----------------------------------------------------------------------
47 * Base addresses -- Note these are effective addresses where the
48 * actual resources get mapped (not physical addresses)
49 *----------------------------------------------------------------------*/
50 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
51 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH */
52 #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
53 #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
55 #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
56 #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
57 #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
59 #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
60 #define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
61 #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
63 #define CFG_PCIE0_CFGBASE 0xc0000000
64 #define CFG_PCIE1_CFGBASE 0xc1000000
65 #define CFG_PCIE2_CFGBASE 0xc2000000
66 #define CFG_PCIE0_XCFGBASE 0xc3000000
67 #define CFG_PCIE1_XCFGBASE 0xc3001000
68 #define CFG_PCIE2_XCFGBASE 0xc3002000
70 /* base address of inbound PCIe window */
71 #define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
73 /* System RAM mapped to PCI space */
74 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
75 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
76 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
78 #define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
80 #define CFG_MONITOR_BASE TEXT_BASE
81 #define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1)
82 #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
84 /*-----------------------------------------------------------------------
85 * Initial RAM & stack pointer (placed in internal SRAM)
86 *----------------------------------------------------------------------*/
87 #define CFG_TEMP_STACK_OCM 1
88 #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
89 #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
90 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
91 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
93 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
94 #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
95 #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
97 /*-----------------------------------------------------------------------
99 *----------------------------------------------------------------------*/
100 #define CONFIG_SERIAL_MULTI 1
101 #undef CONFIG_UART1_CONSOLE
102 #undef CFG_EXT_SERIAL_CLOCK
103 #define CONFIG_BAUDRATE 115200
104 #define CFG_BAUDRATE_TABLE \
105 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
107 /*-----------------------------------------------------------------------
109 *----------------------------------------------------------------------*/
110 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
111 #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
112 #define CONFIG_DDR_ECC 1 /* with ECC support */
113 #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
116 /*-----------------------------------------------------------------------
118 *----------------------------------------------------------------------*/
119 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
120 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
121 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
122 #define CFG_I2C_SLAVE 0x7F
124 #define CONFIG_I2C_MULTI_BUS
125 #define CONFIG_I2C_CMD_TREE
126 #define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */
128 #define IIC0_BOOTPROM_ADDR 0x50
129 #define IIC0_ALT_BOOTPROM_ADDR 0x54
131 #define CFG_I2C_MULTI_EEPROMS
132 #define CFG_I2C_EEPROM_ADDR (0x50)
133 #define CFG_I2C_EEPROM_ADDR_LEN 1
134 #define CFG_EEPROM_PAGE_WRITE_ENABLE
135 #define CFG_EEPROM_PAGE_WRITE_BITS 3
136 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
139 #define CONFIG_RTC_M41T11 1
140 #define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */
141 #define CFG_I2C_RTC_ADDR 0x68
142 #define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */
145 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
146 #define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */
148 * standard dtt sensor configuration - bottom bit will determine local or
149 * remote sensor of the ADM1021, the rest determines index into
150 * CFG_DTT_ADM1021 array below.
152 #define CONFIG_DTT_SENSORS { 0, 1 }
155 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
156 * there will be one entry in this array for each two (dummy) sensors in
157 * CONFIG_DTT_SENSORS.
162 * - conversion rate 0x02 = 0.25 conversions/second
163 * - ALERT ouput disabled
164 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
165 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
167 #define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
169 /*-----------------------------------------------------------------------
171 *----------------------------------------------------------------------*/
172 #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
174 #define CONFIG_PREBOOT "echo;" \
175 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
178 #undef CONFIG_BOOTARGS
180 #define xstr(s) str(s)
183 #define CONFIG_EXTRA_ENV_SETTINGS \
185 "hostname=katmai\0" \
186 "nfsargs=setenv bootargs root=/dev/nfs rw " \
187 "nfsroot=${serverip}:${rootpath}\0" \
188 "ramargs=setenv bootargs root=/dev/ram rw\0" \
189 "addip=setenv bootargs ${bootargs} " \
190 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
191 ":${hostname}:${netdev}:off panic=1\0" \
192 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
193 "flash_nfs=run nfsargs addip addtty;" \
194 "bootm ${kernel_addr}\0" \
195 "flash_self=run ramargs addip addtty;" \
196 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
197 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
199 "net_nfs_fdt=tftp 200000 ${bootfile};" \
200 "tftp ${fdt_addr} ${fdt_file};" \
201 "run nfsargs addip addtty;" \
202 "bootm 200000 - ${fdt_addr}\0" \
203 "rootpath=/opt/eldk/ppc_4xx\0" \
204 "bootfile=katmai/uImage\0" \
205 "fdt_file=katmai/katmai.dtb\0" \
206 "fdt_addr=400000\0" \
207 "kernel_addr=fff10000\0" \
208 "ramdisk_addr=fff20000\0" \
209 "initrd_high=30000000\0" \
210 "load=tftp 200000 katmai/u-boot.bin\0" \
211 "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
212 "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \
213 "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \
214 "setenv filesize;saveenv\0" \
215 "upd=run load update\0" \
216 "kozio=bootm ffc60000\0" \
217 "pciconfighost=1\0" \
218 "pcie_mode=RP:RP:RP\0" \
220 #define CONFIG_BOOTCOMMAND "run flash_self"
222 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
224 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
225 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
231 #define CONFIG_BOOTP_BOOTFILESIZE
232 #define CONFIG_BOOTP_BOOTPATH
233 #define CONFIG_BOOTP_GATEWAY
234 #define CONFIG_BOOTP_HOSTNAME
238 * Command line configuration.
240 #include <config_cmd_default.h>
242 #define CONFIG_CMD_ASKENV
243 #define CONFIG_CMD_EEPROM
244 #define CONFIG_CMD_DATE
245 #define CONFIG_CMD_DHCP
246 #define CONFIG_CMD_DIAG
247 #define CONFIG_CMD_DTT
248 #define CONFIG_CMD_ELF
249 #define CONFIG_CMD_EXT2
250 #define CONFIG_CMD_FAT
251 #define CONFIG_CMD_I2C
252 #define CONFIG_CMD_IRQ
253 #define CONFIG_CMD_MII
254 #define CONFIG_CMD_NET
255 #define CONFIG_CMD_NFS
256 #define CONFIG_CMD_PCI
257 #define CONFIG_CMD_PING
258 #define CONFIG_CMD_REGINFO
259 #define CONFIG_CMD_SDRAM
260 #define CONFIG_CMD_SNTP
262 #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
263 #define CONFIG_MII 1 /* MII PHY management */
264 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
265 #define CONFIG_HAS_ETH0
266 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
267 #define CONFIG_PHY_RESET_DELAY 1000
268 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
269 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
270 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
272 #define CONFIG_NETCONSOLE /* include NetConsole support */
273 #define CONFIG_NET_MULTI /* needed for NetConsole */
275 #undef CONFIG_WATCHDOG /* watchdog disabled */
278 * Miscellaneous configurable options
280 #define CFG_LONGHELP /* undef to save memory */
281 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
283 #if defined(CONFIG_CMD_KGDB)
284 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
286 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
288 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
289 #define CFG_MAXARGS 16 /* max number of command args */
290 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
292 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
293 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
295 #define CFG_LOAD_ADDR 0x100000 /* default load address */
296 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
298 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
300 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
301 #define CONFIG_LOOPW 1 /* enable loopw command */
302 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
303 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
304 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
306 #define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
308 /*-----------------------------------------------------------------------
310 *----------------------------------------------------------------------*/
311 #define CFG_FLASH_CFI
312 #define CFG_FLASH_CFI_DRIVER
313 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
314 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
316 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
317 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
318 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
320 #undef CFG_FLASH_CHECKSUM
321 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
322 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
324 #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
325 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
326 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
328 /* Address and size of Redundant Environment Sector */
329 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
330 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
332 /*-----------------------------------------------------------------------
334 *-----------------------------------------------------------------------
337 #define CONFIG_PCI /* include pci support */
338 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
339 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
340 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
342 /* Board-specific PCI */
343 #define CFG_PCI_TARGET_INIT /* let board init pci target */
344 #undef CFG_PCI_MASTER_INIT
346 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
347 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
348 /* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
351 * NETWORK Support (PCI):
353 /* Support for Intel 82557/82559/82559ER chips. */
354 #define CONFIG_EEPRO100
356 /*-----------------------------------------------------------------------
357 * Xilinx System ACE support
358 *----------------------------------------------------------------------*/
359 #define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
360 #define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
361 #define CFG_SYSTEMACE_BASE CFG_ACE_BASE
362 #define CONFIG_DOS_PARTITION 1
364 /*-----------------------------------------------------------------------
365 * External Bus Controller (EBC) Setup
366 *----------------------------------------------------------------------*/
368 /* Memory Bank 0 (Flash) initialization */
369 #define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
370 EBC_BXAP_TWT_ENCODE(7) | \
371 EBC_BXAP_BCE_DISABLE | \
372 EBC_BXAP_BCT_2TRANS | \
373 EBC_BXAP_CSN_ENCODE(0) | \
374 EBC_BXAP_OEN_ENCODE(0) | \
375 EBC_BXAP_WBN_ENCODE(0) | \
376 EBC_BXAP_WBF_ENCODE(0) | \
377 EBC_BXAP_TH_ENCODE(0) | \
378 EBC_BXAP_RE_DISABLED | \
379 EBC_BXAP_SOR_DELAYED | \
380 EBC_BXAP_BEM_WRITEONLY | \
381 EBC_BXAP_PEN_DISABLED)
382 #define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \
387 /* Memory Bank 1 (Xilinx System ACE controller) initialization */
388 #define CFG_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
389 EBC_BXAP_TWT_ENCODE(4) | \
390 EBC_BXAP_BCE_DISABLE | \
391 EBC_BXAP_BCT_2TRANS | \
392 EBC_BXAP_CSN_ENCODE(0) | \
393 EBC_BXAP_OEN_ENCODE(0) | \
394 EBC_BXAP_WBN_ENCODE(0) | \
395 EBC_BXAP_WBF_ENCODE(0) | \
396 EBC_BXAP_TH_ENCODE(0) | \
397 EBC_BXAP_RE_DISABLED | \
398 EBC_BXAP_SOR_NONDELAYED | \
399 EBC_BXAP_BEM_WRITEONLY | \
400 EBC_BXAP_PEN_DISABLED)
401 #define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \
406 /*-------------------------------------------------------------------------
407 * Initialize EBC CONFIG -
408 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
409 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
410 *-------------------------------------------------------------------------*/
411 #define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \
412 EBC_CFG_PTD_ENABLE | \
413 EBC_CFG_RTC_16PERCLK | \
414 EBC_CFG_ATC_PREVIOUS | \
415 EBC_CFG_DTC_PREVIOUS | \
416 EBC_CFG_CTC_PREVIOUS | \
417 EBC_CFG_OEO_PREVIOUS | \
418 EBC_CFG_EMC_DEFAULT | \
419 EBC_CFG_PME_DISABLE | \
422 /*-----------------------------------------------------------------------
424 *----------------------------------------------------------------------*/
425 #define CFG_GPIO_PCIE_PRESENT0 17
426 #define CFG_GPIO_PCIE_PRESENT1 21
427 #define CFG_GPIO_PCIE_PRESENT2 23
428 #define CFG_GPIO_RS232_FORCEOFF 30
430 #define CFG_PFC0 (GPIO_VAL(CFG_GPIO_PCIE_PRESENT0) | \
431 GPIO_VAL(CFG_GPIO_PCIE_PRESENT1) | \
432 GPIO_VAL(CFG_GPIO_PCIE_PRESENT2) | \
433 GPIO_VAL(CFG_GPIO_RS232_FORCEOFF))
434 #define CFG_GPIO_OR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
435 #define CFG_GPIO_TCR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
436 #define CFG_GPIO_ODR 0
439 * For booting Linux, the board info and command line data
440 * have to be in the first 8 MB of memory, since this is
441 * the maximum mapped by the Linux kernel during initialization.
443 #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
446 * Internal Definitions
450 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
451 #define BOOTFLAG_WARM 0x02 /* Software reboot */
453 #if defined(CONFIG_CMD_KGDB)
454 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
455 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
458 /* pass open firmware flat tree */
459 #define CONFIG_OF_LIBFDT 1
460 #define CONFIG_OF_BOARD_SETUP 1
462 #endif /* __CONFIG_H */